/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include <linux/string.h>
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#include <linux/acpi.h>
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#include <linux/version.h>
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#include <linux/i2c.h>
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#include <drm/drm_probe_helper.h>
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#include <drm/amdgpu_drm.h>
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#include <drm/drm_edid.h>
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#include "dm_services.h"
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#include "amdgpu.h"
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#include "dc.h"
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#include "amdgpu_dm.h"
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#include "amdgpu_dm_irq.h"
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#include "amdgpu_dm_mst_types.h"
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#include "dm_helpers.h"
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/* dm_helpers_parse_edid_caps
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*
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* Parse edid caps
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*
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* @edid: [in] pointer to edid
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* edid_caps: [in] pointer to edid caps
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* @return
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* void
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* */
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enum dc_edid_status dm_helpers_parse_edid_caps(
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struct dc_context *ctx,
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const struct dc_edid *edid,
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struct dc_edid_caps *edid_caps)
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{
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struct edid *edid_buf = (struct edid *) edid->raw_edid;
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struct cea_sad *sads;
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int sad_count = -1;
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int sadb_count = -1;
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int i = 0;
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int j = 0;
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uint8_t *sadb = NULL;
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enum dc_edid_status result = EDID_OK;
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if (!edid_caps || !edid)
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return EDID_BAD_INPUT;
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if (!drm_edid_is_valid(edid_buf))
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result = EDID_BAD_CHECKSUM;
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edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] |
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((uint16_t) edid_buf->mfg_id[1])<<8;
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edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] |
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((uint16_t) edid_buf->prod_code[1])<<8;
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edid_caps->serial_number = edid_buf->serial;
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edid_caps->manufacture_week = edid_buf->mfg_week;
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edid_caps->manufacture_year = edid_buf->mfg_year;
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/* One of the four detailed_timings stores the monitor name. It's
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* stored in an array of length 13. */
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for (i = 0; i < 4; i++) {
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if (edid_buf->detailed_timings[i].data.other_data.type == 0xfc) {
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while (j < 13 && edid_buf->detailed_timings[i].data.other_data.data.str.str[j]) {
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if (edid_buf->detailed_timings[i].data.other_data.data.str.str[j] == '\n')
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break;
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edid_caps->display_name[j] =
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edid_buf->detailed_timings[i].data.other_data.data.str.str[j];
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j++;
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}
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}
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}
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edid_caps->edid_hdmi = drm_detect_hdmi_monitor(
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(struct edid *) edid->raw_edid);
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sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
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if (sad_count <= 0)
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return result;
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edid_caps->audio_mode_count = sad_count < DC_MAX_AUDIO_DESC_COUNT ? sad_count : DC_MAX_AUDIO_DESC_COUNT;
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for (i = 0; i < edid_caps->audio_mode_count; ++i) {
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struct cea_sad *sad = &sads[i];
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edid_caps->audio_modes[i].format_code = sad->format;
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edid_caps->audio_modes[i].channel_count = sad->channels + 1;
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edid_caps->audio_modes[i].sample_rate = sad->freq;
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edid_caps->audio_modes[i].sample_size = sad->byte2;
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}
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sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb);
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if (sadb_count < 0) {
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DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count);
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sadb_count = 0;
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}
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if (sadb_count)
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edid_caps->speaker_flags = sadb[0];
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else
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edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;
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kfree(sads);
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kfree(sadb);
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return result;
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}
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static void get_payload_table(
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struct amdgpu_dm_connector *aconnector,
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struct dp_mst_stream_allocation_table *proposed_table)
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{
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int i;
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struct drm_dp_mst_topology_mgr *mst_mgr =
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&aconnector->mst_port->mst_mgr;
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mutex_lock(&mst_mgr->payload_lock);
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proposed_table->stream_count = 0;
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/* number of active streams */
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for (i = 0; i < mst_mgr->max_payloads; i++) {
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if (mst_mgr->payloads[i].num_slots == 0)
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break; /* end of vcp_id table */
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ASSERT(mst_mgr->payloads[i].payload_state !=
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DP_PAYLOAD_DELETE_LOCAL);
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if (mst_mgr->payloads[i].payload_state == DP_PAYLOAD_LOCAL ||
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mst_mgr->payloads[i].payload_state ==
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DP_PAYLOAD_REMOTE) {
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struct dp_mst_stream_allocation *sa =
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&proposed_table->stream_allocations[
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proposed_table->stream_count];
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sa->slot_count = mst_mgr->payloads[i].num_slots;
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sa->vcp_id = mst_mgr->proposed_vcpis[i]->vcpi;
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proposed_table->stream_count++;
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}
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}
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mutex_unlock(&mst_mgr->payload_lock);
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}
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void dm_helpers_dp_update_branch_info(
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struct dc_context *ctx,
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const struct dc_link *link)
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{}
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/*
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* Writes payload allocation table in immediate downstream device.
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*/
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bool dm_helpers_dp_mst_write_payload_allocation_table(
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struct dc_context *ctx,
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const struct dc_stream_state *stream,
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struct dp_mst_stream_allocation_table *proposed_table,
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bool enable)
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{
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struct amdgpu_dm_connector *aconnector;
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struct dm_connector_state *dm_conn_state;
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struct drm_dp_mst_topology_mgr *mst_mgr;
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struct drm_dp_mst_port *mst_port;
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bool ret;
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aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
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/* Accessing the connector state is required for vcpi_slots allocation
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* and directly relies on behaviour in commit check
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* that blocks before commit guaranteeing that the state
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* is not gonna be swapped while still in use in commit tail */
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if (!aconnector || !aconnector->mst_port)
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return false;
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dm_conn_state = to_dm_connector_state(aconnector->base.state);
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mst_mgr = &aconnector->mst_port->mst_mgr;
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if (!mst_mgr->mst_state)
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return false;
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mst_port = aconnector->port;
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if (enable) {
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ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port,
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dm_conn_state->pbn,
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dm_conn_state->vcpi_slots);
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if (!ret)
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return false;
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} else {
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drm_dp_mst_reset_vcpi_slots(mst_mgr, mst_port);
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}
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/* It's OK for this to fail */
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drm_dp_update_payload_part1(mst_mgr);
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/* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
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* AUX message. The sequence is slot 1-63 allocated sequence for each
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* stream. AMD ASIC stream slot allocation should follow the same
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* sequence. copy DRM MST allocation to dc */
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get_payload_table(aconnector, proposed_table);
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return true;
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}
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/*
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* poll pending down reply
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*/
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void dm_helpers_dp_mst_poll_pending_down_reply(
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struct dc_context *ctx,
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const struct dc_link *link)
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{}
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/*
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* Clear payload allocation table before enable MST DP link.
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*/
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void dm_helpers_dp_mst_clear_payload_allocation_table(
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struct dc_context *ctx,
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const struct dc_link *link)
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{}
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/*
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* Polls for ACT (allocation change trigger) handled and sends
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* ALLOCATE_PAYLOAD message.
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*/
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enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger(
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struct dc_context *ctx,
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const struct dc_stream_state *stream)
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{
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struct amdgpu_dm_connector *aconnector;
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struct drm_dp_mst_topology_mgr *mst_mgr;
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int ret;
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aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
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if (!aconnector || !aconnector->mst_port)
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return ACT_FAILED;
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mst_mgr = &aconnector->mst_port->mst_mgr;
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if (!mst_mgr->mst_state)
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return ACT_FAILED;
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ret = drm_dp_check_act_status(mst_mgr);
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if (ret)
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return ACT_FAILED;
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return ACT_SUCCESS;
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}
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bool dm_helpers_dp_mst_send_payload_allocation(
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struct dc_context *ctx,
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const struct dc_stream_state *stream,
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bool enable)
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{
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struct amdgpu_dm_connector *aconnector;
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struct drm_dp_mst_topology_mgr *mst_mgr;
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struct drm_dp_mst_port *mst_port;
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aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
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if (!aconnector || !aconnector->mst_port)
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return false;
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mst_port = aconnector->port;
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mst_mgr = &aconnector->mst_port->mst_mgr;
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if (!mst_mgr->mst_state)
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return false;
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/* It's OK for this to fail */
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drm_dp_update_payload_part2(mst_mgr);
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if (!enable)
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drm_dp_mst_deallocate_vcpi(mst_mgr, mst_port);
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return true;
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}
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void dm_dtn_log_begin(struct dc_context *ctx,
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struct dc_log_buffer_ctx *log_ctx)
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{
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static const char msg[] = "[dtn begin]\n";
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if (!log_ctx) {
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pr_info("%s", msg);
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return;
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}
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dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);
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}
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void dm_dtn_log_append_v(struct dc_context *ctx,
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struct dc_log_buffer_ctx *log_ctx,
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const char *msg, ...)
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{
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va_list args;
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size_t total;
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int n;
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if (!log_ctx) {
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/* No context, redirect to dmesg. */
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struct va_format vaf;
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vaf.fmt = msg;
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vaf.va = &args;
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va_start(args, msg);
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pr_info("%pV", &vaf);
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va_end(args);
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return;
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}
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/* Measure the output. */
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va_start(args, msg);
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n = vsnprintf(NULL, 0, msg, args);
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va_end(args);
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if (n <= 0)
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return;
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/* Reallocate the string buffer as needed. */
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total = log_ctx->pos + n + 1;
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if (total > log_ctx->size) {
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char *buf = (char *)kvcalloc(total, sizeof(char), GFP_KERNEL);
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if (buf) {
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memcpy(buf, log_ctx->buf, log_ctx->pos);
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kfree(log_ctx->buf);
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log_ctx->buf = buf;
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log_ctx->size = total;
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}
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}
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if (!log_ctx->buf)
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return;
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/* Write the formatted string to the log buffer. */
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va_start(args, msg);
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n = vscnprintf(
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log_ctx->buf + log_ctx->pos,
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log_ctx->size - log_ctx->pos,
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msg,
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args);
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va_end(args);
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if (n > 0)
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log_ctx->pos += n;
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}
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void dm_dtn_log_end(struct dc_context *ctx,
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struct dc_log_buffer_ctx *log_ctx)
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{
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static const char msg[] = "[dtn end]\n";
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if (!log_ctx) {
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pr_info("%s", msg);
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return;
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}
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dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);
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}
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bool dm_helpers_dp_mst_start_top_mgr(
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struct dc_context *ctx,
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const struct dc_link *link,
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bool boot)
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{
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struct amdgpu_dm_connector *aconnector = link->priv;
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if (!aconnector) {
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DRM_ERROR("Failed to find connector for link!");
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return false;
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}
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if (boot) {
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DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n",
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aconnector, aconnector->base.base.id);
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return true;
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}
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DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",
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aconnector, aconnector->base.base.id);
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return (drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true) == 0);
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}
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void dm_helpers_dp_mst_stop_top_mgr(
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struct dc_context *ctx,
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const struct dc_link *link)
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{
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struct amdgpu_dm_connector *aconnector = link->priv;
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if (!aconnector) {
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DRM_ERROR("Failed to find connector for link!");
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return;
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}
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DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n",
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aconnector, aconnector->base.base.id);
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if (aconnector->mst_mgr.mst_state == true)
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drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
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}
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bool dm_helpers_dp_read_dpcd(
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struct dc_context *ctx,
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const struct dc_link *link,
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uint32_t address,
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uint8_t *data,
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uint32_t size)
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{
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struct amdgpu_dm_connector *aconnector = link->priv;
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if (!aconnector) {
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DC_LOG_DC("Failed to find connector for link!\n");
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return false;
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}
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return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address,
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data, size) > 0;
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}
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bool dm_helpers_dp_write_dpcd(
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struct dc_context *ctx,
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const struct dc_link *link,
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uint32_t address,
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const uint8_t *data,
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uint32_t size)
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{
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struct amdgpu_dm_connector *aconnector = link->priv;
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if (!aconnector) {
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DRM_ERROR("Failed to find connector for link!");
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return false;
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}
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return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux,
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address, (uint8_t *)data, size) > 0;
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}
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bool dm_helpers_submit_i2c(
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struct dc_context *ctx,
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const struct dc_link *link,
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struct i2c_command *cmd)
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{
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struct amdgpu_dm_connector *aconnector = link->priv;
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struct i2c_msg *msgs;
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int i = 0;
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int num = cmd->number_of_payloads;
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bool result;
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if (!aconnector) {
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DRM_ERROR("Failed to find connector for link!");
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return false;
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}
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msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL);
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if (!msgs)
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return false;
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for (i = 0; i < num; i++) {
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msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD;
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msgs[i].addr = cmd->payloads[i].address;
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msgs[i].len = cmd->payloads[i].length;
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msgs[i].buf = cmd->payloads[i].data;
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}
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result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num;
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kfree(msgs);
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return result;
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}
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bool dm_helpers_dp_write_dsc_enable(
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struct dc_context *ctx,
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const struct dc_stream_state *stream,
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bool enable
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)
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{
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uint8_t enable_dsc = enable ? 1 : 0;
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struct amdgpu_dm_connector *aconnector;
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if (!stream)
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return false;
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if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
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aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
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if (!aconnector->dsc_aux)
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return false;
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return (drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, &enable_dsc, 1) >= 0);
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}
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if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT)
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return dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
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return false;
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}
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bool dm_helpers_is_dp_sink_present(struct dc_link *link)
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{
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bool dp_sink_present;
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struct amdgpu_dm_connector *aconnector = link->priv;
|
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if (!aconnector) {
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BUG_ON("Failed to find connector for link!");
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return true;
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}
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mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex);
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dp_sink_present = dc_link_is_dp_sink_present(link);
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mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex);
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return dp_sink_present;
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}
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enum dc_edid_status dm_helpers_read_local_edid(
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struct dc_context *ctx,
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struct dc_link *link,
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struct dc_sink *sink)
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{
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struct amdgpu_dm_connector *aconnector = link->priv;
|
struct drm_connector *connector = &aconnector->base;
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struct i2c_adapter *ddc;
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int retry = 3;
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enum dc_edid_status edid_status;
|
struct edid *edid;
|
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if (link->aux_mode)
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ddc = &aconnector->dm_dp_aux.aux.ddc;
|
else
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ddc = &aconnector->i2c->base;
|
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/* some dongles read edid incorrectly the first time,
|
* do check sum and retry to make sure read correct edid.
|
*/
|
do {
|
|
edid = drm_get_edid(&aconnector->base, ddc);
|
|
/* DP Compliance Test 4.2.2.6 */
|
if (link->aux_mode && connector->edid_corrupt)
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drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum);
|
|
if (!edid && connector->edid_corrupt) {
|
connector->edid_corrupt = false;
|
return EDID_BAD_CHECKSUM;
|
}
|
|
if (!edid)
|
return EDID_NO_RESPONSE;
|
|
sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1);
|
memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length);
|
|
/* We don't need the original edid anymore */
|
kfree(edid);
|
|
/* connector->display_info will be parsed from EDID and saved
|
* into drm_connector->display_info from edid by call stack
|
* below:
|
* drm_parse_ycbcr420_deep_color_info
|
* drm_parse_hdmi_forum_vsdb
|
* drm_parse_cea_ext
|
* drm_add_display_info
|
* drm_connector_update_edid_property
|
*
|
* drm_connector->display_info will be used by amdgpu_dm funcs,
|
* like fill_stream_properties_from_drm_display_mode
|
*/
|
amdgpu_dm_update_connector_after_detect(aconnector);
|
|
edid_status = dm_helpers_parse_edid_caps(
|
ctx,
|
&sink->dc_edid,
|
&sink->edid_caps);
|
|
} while (edid_status == EDID_BAD_CHECKSUM && --retry > 0);
|
|
if (edid_status != EDID_OK)
|
DRM_ERROR("EDID err: %d, on connector: %s",
|
edid_status,
|
aconnector->base.name);
|
|
/* DP Compliance Test 4.2.2.3 */
|
if (link->aux_mode)
|
drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, sink->dc_edid.raw_edid[sink->dc_edid.length-1]);
|
|
return edid_status;
|
}
|
|
void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks)
|
{
|
/* TODO: something */
|
}
|
#ifdef CONFIG_DRM_AMD_DC_DCN3_0
|
|
void *dm_helpers_allocate_gpu_mem(
|
struct dc_context *ctx,
|
enum dc_gpu_mem_alloc_type type,
|
size_t size,
|
long long *addr)
|
{
|
// TODO
|
return NULL;
|
}
|
|
void dm_helpers_free_gpu_mem(
|
struct dc_context *ctx,
|
enum dc_gpu_mem_alloc_type type,
|
void *pvMem)
|
{
|
// TODO
|
}
|
#endif
|
