/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
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#define AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
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struct drm_crtc;
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struct dm_crtc_state;
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enum amdgpu_dm_pipe_crc_source {
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AMDGPU_DM_PIPE_CRC_SOURCE_NONE = 0,
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AMDGPU_DM_PIPE_CRC_SOURCE_CRTC,
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AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER,
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AMDGPU_DM_PIPE_CRC_SOURCE_DPRX,
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AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER,
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AMDGPU_DM_PIPE_CRC_SOURCE_MAX,
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AMDGPU_DM_PIPE_CRC_SOURCE_INVALID = -1,
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};
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static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source source)
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{
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return (source > AMDGPU_DM_PIPE_CRC_SOURCE_NONE) &&
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(source < AMDGPU_DM_PIPE_CRC_SOURCE_MAX);
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}
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/* amdgpu_dm_crc.c */
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#ifdef CONFIG_DEBUG_FS
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int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
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struct dm_crtc_state *dm_crtc_state,
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enum amdgpu_dm_pipe_crc_source source);
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int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);
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int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
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const char *src_name,
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size_t *values_cnt);
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const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
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size_t *count);
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void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
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#else
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#define amdgpu_dm_crtc_set_crc_source NULL
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#define amdgpu_dm_crtc_verify_crc_source NULL
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#define amdgpu_dm_crtc_get_crc_sources NULL
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#define amdgpu_dm_crtc_handle_crc_irq(x)
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#endif
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#endif /* AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ */
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