/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include <drm/drm_crtc.h>
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#include <drm/drm_vblank.h>
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#include "amdgpu.h"
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#include "amdgpu_dm.h"
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#include "dc.h"
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static const char *const pipe_crc_sources[] = {
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"none",
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"crtc",
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"crtc dither",
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"dprx",
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"dprx dither",
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"auto",
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};
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static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source)
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{
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if (!source || !strcmp(source, "none"))
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return AMDGPU_DM_PIPE_CRC_SOURCE_NONE;
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if (!strcmp(source, "auto") || !strcmp(source, "crtc"))
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return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC;
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if (!strcmp(source, "dprx"))
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return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX;
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if (!strcmp(source, "crtc dither"))
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return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER;
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if (!strcmp(source, "dprx dither"))
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return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER;
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return AMDGPU_DM_PIPE_CRC_SOURCE_INVALID;
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}
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static bool dm_is_crc_source_crtc(enum amdgpu_dm_pipe_crc_source src)
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{
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return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) ||
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(src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER);
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}
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static bool dm_is_crc_source_dprx(enum amdgpu_dm_pipe_crc_source src)
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{
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return (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX) ||
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(src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER);
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}
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static bool dm_need_crc_dither(enum amdgpu_dm_pipe_crc_source src)
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{
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return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER) ||
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(src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER) ||
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(src == AMDGPU_DM_PIPE_CRC_SOURCE_NONE);
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}
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const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
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size_t *count)
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{
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*count = ARRAY_SIZE(pipe_crc_sources);
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return pipe_crc_sources;
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}
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int
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amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name,
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size_t *values_cnt)
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{
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enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name);
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if (source < 0) {
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DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n",
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src_name, crtc->index);
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return -EINVAL;
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}
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*values_cnt = 3;
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return 0;
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}
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int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
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struct dm_crtc_state *dm_crtc_state,
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enum amdgpu_dm_pipe_crc_source source)
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{
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struct amdgpu_device *adev = drm_to_adev(crtc->dev);
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struct dc_stream_state *stream_state = dm_crtc_state->stream;
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bool enable = amdgpu_dm_is_valid_crc_source(source);
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int ret = 0;
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/* Configuration will be deferred to stream enable. */
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if (!stream_state)
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return 0;
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mutex_lock(&adev->dm.dc_lock);
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/* Enable CRTC CRC generation if necessary. */
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if (dm_is_crc_source_crtc(source) || source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) {
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if (!dc_stream_configure_crc(stream_state->ctx->dc,
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stream_state, enable, enable)) {
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ret = -EINVAL;
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goto unlock;
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}
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}
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/* Configure dithering */
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if (!dm_need_crc_dither(source)) {
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dc_stream_set_dither_option(stream_state, DITHER_OPTION_TRUN8);
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dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state,
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DYN_EXPANSION_DISABLE);
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} else {
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dc_stream_set_dither_option(stream_state,
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DITHER_OPTION_DEFAULT);
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dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state,
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DYN_EXPANSION_AUTO);
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}
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unlock:
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mutex_unlock(&adev->dm.dc_lock);
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return ret;
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}
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int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
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{
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enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name);
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struct drm_crtc_commit *commit;
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struct dm_crtc_state *crtc_state;
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struct drm_dp_aux *aux = NULL;
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bool enable = false;
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bool enabled = false;
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int ret = 0;
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if (source < 0) {
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DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n",
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src_name, crtc->index);
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return -EINVAL;
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}
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ret = drm_modeset_lock(&crtc->mutex, NULL);
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if (ret)
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return ret;
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spin_lock(&crtc->commit_lock);
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commit = list_first_entry_or_null(&crtc->commit_list,
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struct drm_crtc_commit, commit_entry);
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if (commit)
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drm_crtc_commit_get(commit);
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spin_unlock(&crtc->commit_lock);
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if (commit) {
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/*
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* Need to wait for all outstanding programming to complete
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* in commit tail since it can modify CRC related fields and
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* hardware state. Since we're holding the CRTC lock we're
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* guaranteed that no other commit work can be queued off
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* before we modify the state below.
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*/
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ret = wait_for_completion_interruptible_timeout(
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&commit->hw_done, 10 * HZ);
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if (ret)
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goto cleanup;
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}
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enable = amdgpu_dm_is_valid_crc_source(source);
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crtc_state = to_dm_crtc_state(crtc->state);
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/*
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* USER REQ SRC | CURRENT SRC | BEHAVIOR
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* -----------------------------
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* None | None | Do nothing
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* None | CRTC | Disable CRTC CRC, set default to dither
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* None | DPRX | Disable DPRX CRC, need 'aux', set default to dither
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* None | CRTC DITHER | Disable CRTC CRC
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* None | DPRX DITHER | Disable DPRX CRC, need 'aux'
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* CRTC | XXXX | Enable CRTC CRC, no dither
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* DPRX | XXXX | Enable DPRX CRC, need 'aux', no dither
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* CRTC DITHER | XXXX | Enable CRTC CRC, set dither
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* DPRX DITHER | XXXX | Enable DPRX CRC, need 'aux', set dither
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*/
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if (dm_is_crc_source_dprx(source) ||
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(source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE &&
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dm_is_crc_source_dprx(crtc_state->crc_src))) {
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struct amdgpu_dm_connector *aconn = NULL;
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struct drm_connector *connector;
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struct drm_connector_list_iter conn_iter;
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drm_connector_list_iter_begin(crtc->dev, &conn_iter);
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drm_for_each_connector_iter(connector, &conn_iter) {
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if (!connector->state || connector->state->crtc != crtc)
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continue;
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aconn = to_amdgpu_dm_connector(connector);
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break;
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}
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drm_connector_list_iter_end(&conn_iter);
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if (!aconn) {
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DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index);
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ret = -EINVAL;
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goto cleanup;
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}
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aux = &aconn->dm_dp_aux.aux;
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if (!aux) {
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DRM_DEBUG_DRIVER("No dp aux for amd connector\n");
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ret = -EINVAL;
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goto cleanup;
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}
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if ((aconn->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort) &&
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(aconn->base.connector_type != DRM_MODE_CONNECTOR_eDP)) {
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DRM_DEBUG_DRIVER("No DP connector available for CRC source\n");
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ret = -EINVAL;
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goto cleanup;
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}
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}
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if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) {
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ret = -EINVAL;
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goto cleanup;
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}
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/*
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* Reading the CRC requires the vblank interrupt handler to be
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* enabled. Keep a reference until CRC capture stops.
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*/
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enabled = amdgpu_dm_is_valid_crc_source(crtc_state->crc_src);
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if (!enabled && enable) {
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ret = drm_crtc_vblank_get(crtc);
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if (ret)
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goto cleanup;
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if (dm_is_crc_source_dprx(source)) {
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if (drm_dp_start_crc(aux, crtc)) {
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DRM_DEBUG_DRIVER("dp start crc failed\n");
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ret = -EINVAL;
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goto cleanup;
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}
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}
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} else if (enabled && !enable) {
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drm_crtc_vblank_put(crtc);
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if (dm_is_crc_source_dprx(source)) {
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if (drm_dp_stop_crc(aux)) {
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DRM_DEBUG_DRIVER("dp stop crc failed\n");
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ret = -EINVAL;
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goto cleanup;
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}
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}
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}
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crtc_state->crc_src = source;
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/* Reset crc_skipped on dm state */
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crtc_state->crc_skip_count = 0;
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cleanup:
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if (commit)
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drm_crtc_commit_put(commit);
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drm_modeset_unlock(&crtc->mutex);
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return ret;
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}
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/**
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* amdgpu_dm_crtc_handle_crc_irq: Report to DRM the CRC on given CRTC.
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* @crtc: DRM CRTC object.
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*
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* This function should be called at the end of a vblank, when the fb has been
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* fully processed through the pipe.
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*/
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void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc)
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{
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struct dm_crtc_state *crtc_state;
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struct dc_stream_state *stream_state;
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uint32_t crcs[3];
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if (crtc == NULL)
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return;
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crtc_state = to_dm_crtc_state(crtc->state);
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stream_state = crtc_state->stream;
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/* Early return if CRC capture is not enabled. */
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if (!amdgpu_dm_is_valid_crc_source(crtc_state->crc_src))
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return;
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/*
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* Since flipping and crc enablement happen asynchronously, we - more
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* often than not - will be returning an 'uncooked' crc on first frame.
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* Probably because hw isn't ready yet. For added security, skip the
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* first two CRC values.
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*/
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if (crtc_state->crc_skip_count < 2) {
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crtc_state->crc_skip_count += 1;
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return;
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}
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if (dm_is_crc_source_crtc(crtc_state->crc_src)) {
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if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state,
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&crcs[0], &crcs[1], &crcs[2]))
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return;
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drm_crtc_add_crc_entry(crtc, true,
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drm_crtc_accurate_vblank_count(crtc), crcs);
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}
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}
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