/*
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*
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* (C) COPYRIGHT 2014-2016 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU licence.
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*
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* A copy of the licence is included with the program, and can also be obtained
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* from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA.
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*
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*/
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#include <mali_kbase.h>
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#include <mali_kbase_hwaccess_time.h>
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#include <backend/gpu/mali_kbase_device_internal.h>
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#include <backend/gpu/mali_kbase_pm_internal.h>
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void kbase_backend_get_gpu_time(struct kbase_device *kbdev, u64 *cycle_counter,
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u64 *system_time, struct timespec64 *ts)
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{
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u32 hi1, hi2;
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kbase_pm_request_gpu_cycle_counter(kbdev);
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/* Read hi, lo, hi to ensure that overflow from lo to hi is handled
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* correctly */
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do {
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hi1 = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_HI),
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NULL);
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*cycle_counter = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(CYCLE_COUNT_LO), NULL);
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hi2 = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_HI),
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NULL);
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*cycle_counter |= (((u64) hi1) << 32);
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} while (hi1 != hi2);
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/* Read hi, lo, hi to ensure that overflow from lo to hi is handled
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* correctly */
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do {
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hi1 = kbase_reg_read(kbdev, GPU_CONTROL_REG(TIMESTAMP_HI),
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NULL);
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*system_time = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(TIMESTAMP_LO), NULL);
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hi2 = kbase_reg_read(kbdev, GPU_CONTROL_REG(TIMESTAMP_HI),
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NULL);
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*system_time |= (((u64) hi1) << 32);
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} while (hi1 != hi2);
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/* Record the CPU's idea of current time */
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ktime_get_raw_ts64(ts);
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kbase_pm_release_gpu_cycle_counter(kbdev);
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}
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/**
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* kbase_wait_write_flush - Wait for GPU write flush
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* @kctx: Context pointer
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*
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* Wait 1000 GPU clock cycles. This delay is known to give the GPU time to flush
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* its write buffer.
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*
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* Only in use for BASE_HW_ISSUE_6367
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*
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* Note : If GPU resets occur then the counters are reset to zero, the delay may
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* not be as expected.
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*/
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#ifndef CONFIG_MALI_NO_MALI
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void kbase_wait_write_flush(struct kbase_context *kctx)
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{
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u32 base_count = 0;
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/*
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* The caller must be holding onto the kctx or the call is from
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* userspace.
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*/
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kbase_pm_context_active(kctx->kbdev);
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kbase_pm_request_gpu_cycle_counter(kctx->kbdev);
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while (true) {
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u32 new_count;
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new_count = kbase_reg_read(kctx->kbdev,
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GPU_CONTROL_REG(CYCLE_COUNT_LO), NULL);
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/* First time around, just store the count. */
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if (base_count == 0) {
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base_count = new_count;
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continue;
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}
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/* No need to handle wrapping, unsigned maths works for this. */
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if ((new_count - base_count) > 1000)
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break;
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}
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kbase_pm_release_gpu_cycle_counter(kctx->kbdev);
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kbase_pm_context_idle(kctx->kbdev);
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}
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#endif /* CONFIG_MALI_NO_MALI */
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