/*
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*
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* (C) COPYRIGHT 2010-2016 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU licence.
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*
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* A copy of the licence is included with the program, and can also be obtained
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* from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA.
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*
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*/
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/*
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* GPU backend implementation of base kernel power management APIs
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*/
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#include <mali_kbase.h>
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#include <mali_midg_regmap.h>
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#include <mali_kbase_config_defaults.h>
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#ifdef CONFIG_MALI_PLATFORM_DEVICETREE
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#include <linux/pm_runtime.h>
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#endif /* CONFIG_MALI_PLATFORM_DEVICETREE */
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#include <mali_kbase_pm.h>
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#include <mali_kbase_hwaccess_jm.h>
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#include <backend/gpu/mali_kbase_js_internal.h>
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#include <backend/gpu/mali_kbase_pm_internal.h>
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#include <backend/gpu/mali_kbase_device_internal.h>
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#include <backend/gpu/mali_kbase_jm_internal.h>
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static void kbase_pm_gpu_poweroff_wait_wq(struct work_struct *data);
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void kbase_pm_register_access_enable(struct kbase_device *kbdev)
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{
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struct kbase_pm_callback_conf *callbacks;
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callbacks = (struct kbase_pm_callback_conf *)POWER_MANAGEMENT_CALLBACKS;
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if (callbacks)
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callbacks->power_on_callback(kbdev);
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kbdev->pm.backend.gpu_powered = true;
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}
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void kbase_pm_register_access_disable(struct kbase_device *kbdev)
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{
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struct kbase_pm_callback_conf *callbacks;
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callbacks = (struct kbase_pm_callback_conf *)POWER_MANAGEMENT_CALLBACKS;
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if (callbacks)
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callbacks->power_off_callback(kbdev);
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kbdev->pm.backend.gpu_powered = false;
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}
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int kbase_hwaccess_pm_init(struct kbase_device *kbdev)
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{
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int ret = 0;
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struct kbase_pm_callback_conf *callbacks;
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KBASE_DEBUG_ASSERT(kbdev != NULL);
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mutex_init(&kbdev->pm.lock);
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kbdev->pm.backend.gpu_poweroff_wait_wq = alloc_workqueue("kbase_pm_poweroff_wait",
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WQ_HIGHPRI | WQ_UNBOUND, 1);
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if (!kbdev->pm.backend.gpu_poweroff_wait_wq)
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return -ENOMEM;
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INIT_WORK(&kbdev->pm.backend.gpu_poweroff_wait_work,
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kbase_pm_gpu_poweroff_wait_wq);
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kbdev->pm.backend.gpu_powered = false;
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kbdev->pm.suspending = false;
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#ifdef CONFIG_MALI_DEBUG
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kbdev->pm.backend.driver_ready_for_irqs = false;
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#endif /* CONFIG_MALI_DEBUG */
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kbdev->pm.backend.gpu_in_desired_state = true;
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init_waitqueue_head(&kbdev->pm.backend.gpu_in_desired_state_wait);
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callbacks = (struct kbase_pm_callback_conf *)POWER_MANAGEMENT_CALLBACKS;
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if (callbacks) {
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kbdev->pm.backend.callback_power_on =
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callbacks->power_on_callback;
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kbdev->pm.backend.callback_power_off =
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callbacks->power_off_callback;
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kbdev->pm.backend.callback_power_suspend =
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callbacks->power_suspend_callback;
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kbdev->pm.backend.callback_power_resume =
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callbacks->power_resume_callback;
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kbdev->pm.callback_power_runtime_init =
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callbacks->power_runtime_init_callback;
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kbdev->pm.callback_power_runtime_term =
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callbacks->power_runtime_term_callback;
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kbdev->pm.backend.callback_power_runtime_on =
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callbacks->power_runtime_on_callback;
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kbdev->pm.backend.callback_power_runtime_off =
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callbacks->power_runtime_off_callback;
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kbdev->pm.backend.callback_power_runtime_idle =
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callbacks->power_runtime_idle_callback;
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} else {
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kbdev->pm.backend.callback_power_on = NULL;
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kbdev->pm.backend.callback_power_off = NULL;
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kbdev->pm.backend.callback_power_suspend = NULL;
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kbdev->pm.backend.callback_power_resume = NULL;
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kbdev->pm.callback_power_runtime_init = NULL;
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kbdev->pm.callback_power_runtime_term = NULL;
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kbdev->pm.backend.callback_power_runtime_on = NULL;
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kbdev->pm.backend.callback_power_runtime_off = NULL;
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kbdev->pm.backend.callback_power_runtime_idle = NULL;
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}
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/* Initialise the metrics subsystem */
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ret = kbasep_pm_metrics_init(kbdev);
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if (ret)
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return ret;
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init_waitqueue_head(&kbdev->pm.backend.l2_powered_wait);
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kbdev->pm.backend.l2_powered = 0;
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init_waitqueue_head(&kbdev->pm.backend.reset_done_wait);
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kbdev->pm.backend.reset_done = false;
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init_waitqueue_head(&kbdev->pm.zero_active_count_wait);
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kbdev->pm.active_count = 0;
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spin_lock_init(&kbdev->pm.backend.gpu_cycle_counter_requests_lock);
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spin_lock_init(&kbdev->pm.backend.gpu_powered_lock);
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init_waitqueue_head(&kbdev->pm.backend.poweroff_wait);
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if (kbase_pm_ca_init(kbdev) != 0)
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goto workq_fail;
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if (kbase_pm_policy_init(kbdev) != 0)
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goto pm_policy_fail;
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return 0;
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pm_policy_fail:
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kbase_pm_ca_term(kbdev);
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workq_fail:
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kbasep_pm_metrics_term(kbdev);
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return -EINVAL;
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}
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void kbase_pm_do_poweron(struct kbase_device *kbdev, bool is_resume)
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{
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lockdep_assert_held(&kbdev->pm.lock);
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/* Turn clocks and interrupts on - no-op if we haven't done a previous
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* kbase_pm_clock_off() */
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kbase_pm_clock_on(kbdev, is_resume);
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/* Update core status as required by the policy */
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KBASE_TIMELINE_PM_CHECKTRANS(kbdev,
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SW_FLOW_PM_CHECKTRANS_PM_DO_POWERON_START);
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kbase_pm_update_cores_state(kbdev);
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KBASE_TIMELINE_PM_CHECKTRANS(kbdev,
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SW_FLOW_PM_CHECKTRANS_PM_DO_POWERON_END);
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/* NOTE: We don't wait to reach the desired state, since running atoms
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* will wait for that state to be reached anyway */
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}
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static void kbase_pm_gpu_poweroff_wait_wq(struct work_struct *data)
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{
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struct kbase_device *kbdev = container_of(data, struct kbase_device,
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pm.backend.gpu_poweroff_wait_work);
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struct kbase_pm_device_data *pm = &kbdev->pm;
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struct kbase_pm_backend_data *backend = &pm->backend;
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struct kbasep_js_device_data *js_devdata = &kbdev->js_data;
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unsigned long flags;
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#if !PLATFORM_POWER_DOWN_ONLY
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/* Wait for power transitions to complete. We do this with no locks held
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* so that we don't deadlock with any pending workqueues */
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KBASE_TIMELINE_PM_CHECKTRANS(kbdev,
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SW_FLOW_PM_CHECKTRANS_PM_DO_POWEROFF_START);
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kbase_pm_check_transitions_sync(kbdev);
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KBASE_TIMELINE_PM_CHECKTRANS(kbdev,
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SW_FLOW_PM_CHECKTRANS_PM_DO_POWEROFF_END);
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#endif /* !PLATFORM_POWER_DOWN_ONLY */
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mutex_lock(&js_devdata->runpool_mutex);
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mutex_lock(&kbdev->pm.lock);
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#if PLATFORM_POWER_DOWN_ONLY
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if (kbdev->pm.backend.gpu_powered) {
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if (kbase_pm_get_ready_cores(kbdev, KBASE_PM_CORE_L2)) {
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/* If L2 cache is powered then we must flush it before
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* we power off the GPU. Normally this would have been
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* handled when the L2 was powered off. */
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kbase_gpu_cacheclean(kbdev);
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}
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}
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#endif /* PLATFORM_POWER_DOWN_ONLY */
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if (!backend->poweron_required) {
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#if !PLATFORM_POWER_DOWN_ONLY
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unsigned long flags;
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spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
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WARN_ON(kbdev->l2_available_bitmap ||
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kbdev->shader_available_bitmap ||
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kbdev->tiler_available_bitmap);
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spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
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#endif /* !PLATFORM_POWER_DOWN_ONLY */
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/* Consume any change-state events */
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kbase_timeline_pm_check_handle_event(kbdev,
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KBASE_TIMELINE_PM_EVENT_GPU_STATE_CHANGED);
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/* Disable interrupts and turn the clock off */
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if (!kbase_pm_clock_off(kbdev, backend->poweroff_is_suspend)) {
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/*
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* Page/bus faults are pending, must drop locks to
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* process. Interrupts are disabled so no more faults
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* should be generated at this point.
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*/
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mutex_unlock(&kbdev->pm.lock);
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mutex_unlock(&js_devdata->runpool_mutex);
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kbase_flush_mmu_wqs(kbdev);
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mutex_lock(&js_devdata->runpool_mutex);
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mutex_lock(&kbdev->pm.lock);
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/* Turn off clock now that fault have been handled. We
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* dropped locks so poweron_required may have changed -
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* power back on if this is the case.*/
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if (backend->poweron_required)
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kbase_pm_clock_on(kbdev, false);
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else
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WARN_ON(!kbase_pm_clock_off(kbdev,
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backend->poweroff_is_suspend));
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}
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}
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spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
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backend->poweroff_wait_in_progress = false;
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if (backend->poweron_required) {
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backend->poweron_required = false;
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kbase_pm_update_cores_state_nolock(kbdev);
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kbase_backend_slot_update(kbdev);
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}
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spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
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mutex_unlock(&kbdev->pm.lock);
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mutex_unlock(&js_devdata->runpool_mutex);
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wake_up(&kbdev->pm.backend.poweroff_wait);
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}
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void kbase_pm_do_poweroff(struct kbase_device *kbdev, bool is_suspend)
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{
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unsigned long flags;
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lockdep_assert_held(&kbdev->pm.lock);
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spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
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if (!kbdev->pm.backend.poweroff_wait_in_progress) {
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/* Force all cores off */
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kbdev->pm.backend.desired_shader_state = 0;
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kbdev->pm.backend.desired_tiler_state = 0;
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/* Force all cores to be unavailable, in the situation where
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* transitions are in progress for some cores but not others,
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* and kbase_pm_check_transitions_nolock can not immediately
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* power off the cores */
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kbdev->shader_available_bitmap = 0;
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kbdev->tiler_available_bitmap = 0;
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kbdev->l2_available_bitmap = 0;
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kbdev->pm.backend.poweroff_wait_in_progress = true;
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kbdev->pm.backend.poweroff_is_suspend = is_suspend;
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spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
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/*Kick off wq here. Callers will have to wait*/
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queue_work(kbdev->pm.backend.gpu_poweroff_wait_wq,
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&kbdev->pm.backend.gpu_poweroff_wait_work);
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} else {
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spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
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}
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}
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static bool is_poweroff_in_progress(struct kbase_device *kbdev)
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{
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bool ret;
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unsigned long flags;
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spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
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ret = (kbdev->pm.backend.poweroff_wait_in_progress == false);
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spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
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return ret;
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}
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void kbase_pm_wait_for_poweroff_complete(struct kbase_device *kbdev)
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{
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wait_event_killable(kbdev->pm.backend.poweroff_wait,
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is_poweroff_in_progress(kbdev));
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}
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int kbase_hwaccess_pm_powerup(struct kbase_device *kbdev,
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unsigned int flags)
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{
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struct kbasep_js_device_data *js_devdata = &kbdev->js_data;
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unsigned long irq_flags;
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int ret;
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KBASE_DEBUG_ASSERT(kbdev != NULL);
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mutex_lock(&js_devdata->runpool_mutex);
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mutex_lock(&kbdev->pm.lock);
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/* A suspend won't happen during startup/insmod */
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KBASE_DEBUG_ASSERT(!kbase_pm_is_suspending(kbdev));
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/* Power up the GPU, don't enable IRQs as we are not ready to receive
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* them. */
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ret = kbase_pm_init_hw(kbdev, flags);
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if (ret) {
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mutex_unlock(&kbdev->pm.lock);
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mutex_unlock(&js_devdata->runpool_mutex);
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return ret;
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}
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kbasep_pm_init_core_use_bitmaps(kbdev);
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kbdev->pm.debug_core_mask_all = kbdev->pm.debug_core_mask[0] =
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kbdev->pm.debug_core_mask[1] =
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kbdev->pm.debug_core_mask[2] =
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kbdev->gpu_props.props.raw_props.shader_present;
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/* Pretend the GPU is active to prevent a power policy turning the GPU
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* cores off */
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kbdev->pm.active_count = 1;
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spin_lock_irqsave(&kbdev->pm.backend.gpu_cycle_counter_requests_lock,
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irq_flags);
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/* Ensure cycle counter is off */
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kbdev->pm.backend.gpu_cycle_counter_requests = 0;
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spin_unlock_irqrestore(
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&kbdev->pm.backend.gpu_cycle_counter_requests_lock,
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irq_flags);
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/* We are ready to receive IRQ's now as power policy is set up, so
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* enable them now. */
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#ifdef CONFIG_MALI_DEBUG
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spin_lock_irqsave(&kbdev->pm.backend.gpu_powered_lock, irq_flags);
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kbdev->pm.backend.driver_ready_for_irqs = true;
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spin_unlock_irqrestore(&kbdev->pm.backend.gpu_powered_lock, irq_flags);
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#endif
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kbase_pm_enable_interrupts(kbdev);
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/* Turn on the GPU and any cores needed by the policy */
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kbase_pm_do_poweron(kbdev, false);
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mutex_unlock(&kbdev->pm.lock);
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mutex_unlock(&js_devdata->runpool_mutex);
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/* Idle the GPU and/or cores, if the policy wants it to */
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kbase_pm_context_idle(kbdev);
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return 0;
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}
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void kbase_hwaccess_pm_halt(struct kbase_device *kbdev)
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{
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KBASE_DEBUG_ASSERT(kbdev != NULL);
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mutex_lock(&kbdev->pm.lock);
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kbase_pm_cancel_deferred_poweroff(kbdev);
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kbase_pm_do_poweroff(kbdev, false);
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mutex_unlock(&kbdev->pm.lock);
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}
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KBASE_EXPORT_TEST_API(kbase_hwaccess_pm_halt);
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void kbase_hwaccess_pm_term(struct kbase_device *kbdev)
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{
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KBASE_DEBUG_ASSERT(kbdev != NULL);
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KBASE_DEBUG_ASSERT(kbdev->pm.active_count == 0);
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KBASE_DEBUG_ASSERT(kbdev->pm.backend.gpu_cycle_counter_requests == 0);
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/* Free any resources the policy allocated */
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kbase_pm_policy_term(kbdev);
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kbase_pm_ca_term(kbdev);
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/* Shut down the metrics subsystem */
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kbasep_pm_metrics_term(kbdev);
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destroy_workqueue(kbdev->pm.backend.gpu_poweroff_wait_wq);
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}
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void kbase_pm_power_changed(struct kbase_device *kbdev)
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{
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bool cores_are_available;
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unsigned long flags;
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KBASE_TIMELINE_PM_CHECKTRANS(kbdev,
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SW_FLOW_PM_CHECKTRANS_GPU_INTERRUPT_START);
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spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
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cores_are_available = kbase_pm_check_transitions_nolock(kbdev);
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KBASE_TIMELINE_PM_CHECKTRANS(kbdev,
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SW_FLOW_PM_CHECKTRANS_GPU_INTERRUPT_END);
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if (cores_are_available) {
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/* Log timelining information that a change in state has
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* completed */
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kbase_timeline_pm_handle_event(kbdev,
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KBASE_TIMELINE_PM_EVENT_GPU_STATE_CHANGED);
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kbase_backend_slot_update(kbdev);
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}
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spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
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}
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void kbase_pm_set_debug_core_mask(struct kbase_device *kbdev,
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u64 new_core_mask_js0, u64 new_core_mask_js1,
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u64 new_core_mask_js2)
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{
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kbdev->pm.debug_core_mask[0] = new_core_mask_js0;
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kbdev->pm.debug_core_mask[1] = new_core_mask_js1;
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kbdev->pm.debug_core_mask[2] = new_core_mask_js2;
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kbdev->pm.debug_core_mask_all = new_core_mask_js0 | new_core_mask_js1 |
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new_core_mask_js2;
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kbase_pm_update_cores_state_nolock(kbdev);
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}
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void kbase_hwaccess_pm_gpu_active(struct kbase_device *kbdev)
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{
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kbase_pm_update_active(kbdev);
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}
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void kbase_hwaccess_pm_gpu_idle(struct kbase_device *kbdev)
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{
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kbase_pm_update_active(kbdev);
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}
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void kbase_hwaccess_pm_suspend(struct kbase_device *kbdev)
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{
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struct kbasep_js_device_data *js_devdata = &kbdev->js_data;
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/* Force power off the GPU and all cores (regardless of policy), only
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* after the PM active count reaches zero (otherwise, we risk turning it
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* off prematurely) */
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mutex_lock(&js_devdata->runpool_mutex);
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mutex_lock(&kbdev->pm.lock);
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kbase_pm_cancel_deferred_poweroff(kbdev);
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kbase_pm_do_poweroff(kbdev, true);
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kbase_backend_timer_suspend(kbdev);
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mutex_unlock(&kbdev->pm.lock);
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mutex_unlock(&js_devdata->runpool_mutex);
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kbase_pm_wait_for_poweroff_complete(kbdev);
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}
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void kbase_hwaccess_pm_resume(struct kbase_device *kbdev)
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{
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struct kbasep_js_device_data *js_devdata = &kbdev->js_data;
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mutex_lock(&js_devdata->runpool_mutex);
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mutex_lock(&kbdev->pm.lock);
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kbdev->pm.suspending = false;
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kbase_pm_do_poweron(kbdev, true);
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kbase_backend_timer_resume(kbdev);
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mutex_unlock(&kbdev->pm.lock);
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mutex_unlock(&js_devdata->runpool_mutex);
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}
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