/*
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*
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* (C) COPYRIGHT 2014-2016 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU licence.
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*
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* A copy of the licence is included with the program, and can also be obtained
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* from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA.
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*
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*/
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#include <mali_kbase.h>
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#include <backend/gpu/mali_kbase_device_internal.h>
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#include <backend/gpu/mali_kbase_irq_internal.h>
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#include <linux/interrupt.h>
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#if !defined(CONFIG_MALI_NO_MALI)
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/* GPU IRQ Tags */
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#define JOB_IRQ_TAG 0
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#define MMU_IRQ_TAG 1
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#define GPU_IRQ_TAG 2
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static void *kbase_tag(void *ptr, u32 tag)
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{
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return (void *)(((uintptr_t) ptr) | tag);
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}
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static void *kbase_untag(void *ptr)
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{
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return (void *)(((uintptr_t) ptr) & ~3);
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}
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static irqreturn_t kbase_job_irq_handler(int irq, void *data)
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{
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unsigned long flags;
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struct kbase_device *kbdev = kbase_untag(data);
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u32 val;
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spin_lock_irqsave(&kbdev->pm.backend.gpu_powered_lock, flags);
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if (!kbdev->pm.backend.gpu_powered) {
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/* GPU is turned off - IRQ is not for us */
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spin_unlock_irqrestore(&kbdev->pm.backend.gpu_powered_lock,
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flags);
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return IRQ_NONE;
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}
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val = kbase_reg_read(kbdev, JOB_CONTROL_REG(JOB_IRQ_STATUS), NULL);
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#ifdef CONFIG_MALI_DEBUG
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if (!kbdev->pm.backend.driver_ready_for_irqs)
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dev_warn(kbdev->dev, "%s: irq %d irqstatus 0x%x before driver is ready\n",
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__func__, irq, val);
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#endif /* CONFIG_MALI_DEBUG */
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spin_unlock_irqrestore(&kbdev->pm.backend.gpu_powered_lock, flags);
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if (!val)
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return IRQ_NONE;
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dev_dbg(kbdev->dev, "%s: irq %d irqstatus 0x%x\n", __func__, irq, val);
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kbase_job_done(kbdev, val);
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return IRQ_HANDLED;
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}
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KBASE_EXPORT_TEST_API(kbase_job_irq_handler);
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static irqreturn_t kbase_mmu_irq_handler(int irq, void *data)
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{
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unsigned long flags;
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struct kbase_device *kbdev = kbase_untag(data);
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u32 val;
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spin_lock_irqsave(&kbdev->pm.backend.gpu_powered_lock, flags);
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if (!kbdev->pm.backend.gpu_powered) {
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/* GPU is turned off - IRQ is not for us */
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spin_unlock_irqrestore(&kbdev->pm.backend.gpu_powered_lock,
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flags);
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return IRQ_NONE;
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}
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atomic_inc(&kbdev->faults_pending);
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val = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_STATUS), NULL);
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#ifdef CONFIG_MALI_DEBUG
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if (!kbdev->pm.backend.driver_ready_for_irqs)
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dev_warn(kbdev->dev, "%s: irq %d irqstatus 0x%x before driver is ready\n",
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__func__, irq, val);
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#endif /* CONFIG_MALI_DEBUG */
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spin_unlock_irqrestore(&kbdev->pm.backend.gpu_powered_lock, flags);
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if (!val) {
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atomic_dec(&kbdev->faults_pending);
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return IRQ_NONE;
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}
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dev_dbg(kbdev->dev, "%s: irq %d irqstatus 0x%x\n", __func__, irq, val);
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kbase_mmu_interrupt(kbdev, val);
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atomic_dec(&kbdev->faults_pending);
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return IRQ_HANDLED;
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}
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static irqreturn_t kbase_gpu_irq_handler(int irq, void *data)
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{
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unsigned long flags;
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struct kbase_device *kbdev = kbase_untag(data);
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u32 val;
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spin_lock_irqsave(&kbdev->pm.backend.gpu_powered_lock, flags);
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if (!kbdev->pm.backend.gpu_powered) {
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/* GPU is turned off - IRQ is not for us */
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spin_unlock_irqrestore(&kbdev->pm.backend.gpu_powered_lock,
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flags);
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return IRQ_NONE;
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}
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val = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_STATUS), NULL);
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#ifdef CONFIG_MALI_DEBUG
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if (!kbdev->pm.backend.driver_ready_for_irqs)
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dev_dbg(kbdev->dev, "%s: irq %d irqstatus 0x%x before driver is ready\n",
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__func__, irq, val);
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#endif /* CONFIG_MALI_DEBUG */
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spin_unlock_irqrestore(&kbdev->pm.backend.gpu_powered_lock, flags);
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if (!val)
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return IRQ_NONE;
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dev_dbg(kbdev->dev, "%s: irq %d irqstatus 0x%x\n", __func__, irq, val);
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kbase_gpu_interrupt(kbdev, val);
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return IRQ_HANDLED;
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}
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KBASE_EXPORT_TEST_API(kbase_gpu_irq_handler);
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static irq_handler_t kbase_handler_table[] = {
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[JOB_IRQ_TAG] = kbase_job_irq_handler,
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[MMU_IRQ_TAG] = kbase_mmu_irq_handler,
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[GPU_IRQ_TAG] = kbase_gpu_irq_handler,
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};
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#ifdef CONFIG_MALI_DEBUG
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#define JOB_IRQ_HANDLER JOB_IRQ_TAG
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#define MMU_IRQ_HANDLER MMU_IRQ_TAG
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#define GPU_IRQ_HANDLER GPU_IRQ_TAG
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/**
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* kbase_set_custom_irq_handler - Set a custom IRQ handler
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* @kbdev: Device for which the handler is to be registered
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* @custom_handler: Handler to be registered
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* @irq_type: Interrupt type
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*
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* Registers given interrupt handler for requested interrupt type
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* In the case where irq handler is not specified, the default handler shall be
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* registered
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*
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* Return: 0 case success, error code otherwise
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*/
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int kbase_set_custom_irq_handler(struct kbase_device *kbdev,
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irq_handler_t custom_handler,
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int irq_type)
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{
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int result = 0;
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irq_handler_t requested_irq_handler = NULL;
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KBASE_DEBUG_ASSERT((JOB_IRQ_HANDLER <= irq_type) &&
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(GPU_IRQ_HANDLER >= irq_type));
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/* Release previous handler */
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if (kbdev->irqs[irq_type].irq)
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free_irq(kbdev->irqs[irq_type].irq, kbase_tag(kbdev, irq_type));
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requested_irq_handler = (NULL != custom_handler) ? custom_handler :
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kbase_handler_table[irq_type];
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if (0 != request_irq(kbdev->irqs[irq_type].irq,
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requested_irq_handler,
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kbdev->irqs[irq_type].flags | IRQF_SHARED,
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dev_name(kbdev->dev), kbase_tag(kbdev, irq_type))) {
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result = -EINVAL;
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dev_err(kbdev->dev, "Can't request interrupt %d (index %d)\n",
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kbdev->irqs[irq_type].irq, irq_type);
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#ifdef CONFIG_SPARSE_IRQ
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dev_err(kbdev->dev, "You have CONFIG_SPARSE_IRQ support enabled - is the interrupt number correct for this configuration?\n");
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#endif /* CONFIG_SPARSE_IRQ */
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}
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return result;
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}
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KBASE_EXPORT_TEST_API(kbase_set_custom_irq_handler);
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/* test correct interrupt assigment and reception by cpu */
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struct kbasep_irq_test {
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struct hrtimer timer;
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wait_queue_head_t wait;
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int triggered;
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u32 timeout;
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};
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static struct kbasep_irq_test kbasep_irq_test_data;
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#define IRQ_TEST_TIMEOUT 500
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static irqreturn_t kbase_job_irq_test_handler(int irq, void *data)
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{
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unsigned long flags;
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struct kbase_device *kbdev = kbase_untag(data);
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u32 val;
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spin_lock_irqsave(&kbdev->pm.backend.gpu_powered_lock, flags);
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if (!kbdev->pm.backend.gpu_powered) {
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/* GPU is turned off - IRQ is not for us */
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spin_unlock_irqrestore(&kbdev->pm.backend.gpu_powered_lock,
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flags);
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return IRQ_NONE;
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}
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val = kbase_reg_read(kbdev, JOB_CONTROL_REG(JOB_IRQ_STATUS), NULL);
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spin_unlock_irqrestore(&kbdev->pm.backend.gpu_powered_lock, flags);
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if (!val)
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return IRQ_NONE;
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dev_dbg(kbdev->dev, "%s: irq %d irqstatus 0x%x\n", __func__, irq, val);
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kbasep_irq_test_data.triggered = 1;
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wake_up(&kbasep_irq_test_data.wait);
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kbase_reg_write(kbdev, JOB_CONTROL_REG(JOB_IRQ_CLEAR), val, NULL);
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return IRQ_HANDLED;
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}
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static irqreturn_t kbase_mmu_irq_test_handler(int irq, void *data)
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{
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unsigned long flags;
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struct kbase_device *kbdev = kbase_untag(data);
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u32 val;
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spin_lock_irqsave(&kbdev->pm.backend.gpu_powered_lock, flags);
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if (!kbdev->pm.backend.gpu_powered) {
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/* GPU is turned off - IRQ is not for us */
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spin_unlock_irqrestore(&kbdev->pm.backend.gpu_powered_lock,
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flags);
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return IRQ_NONE;
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}
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val = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_STATUS), NULL);
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spin_unlock_irqrestore(&kbdev->pm.backend.gpu_powered_lock, flags);
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if (!val)
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return IRQ_NONE;
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dev_dbg(kbdev->dev, "%s: irq %d irqstatus 0x%x\n", __func__, irq, val);
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kbasep_irq_test_data.triggered = 1;
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wake_up(&kbasep_irq_test_data.wait);
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kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), val, NULL);
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return IRQ_HANDLED;
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}
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static enum hrtimer_restart kbasep_test_interrupt_timeout(struct hrtimer *timer)
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{
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struct kbasep_irq_test *test_data = container_of(timer,
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struct kbasep_irq_test, timer);
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test_data->timeout = 1;
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test_data->triggered = 1;
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wake_up(&test_data->wait);
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return HRTIMER_NORESTART;
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}
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static int kbasep_common_test_interrupt(
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struct kbase_device * const kbdev, u32 tag)
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{
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int err = 0;
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irq_handler_t test_handler;
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u32 old_mask_val;
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u16 mask_offset;
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u16 rawstat_offset;
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switch (tag) {
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case JOB_IRQ_TAG:
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test_handler = kbase_job_irq_test_handler;
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rawstat_offset = JOB_CONTROL_REG(JOB_IRQ_RAWSTAT);
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mask_offset = JOB_CONTROL_REG(JOB_IRQ_MASK);
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break;
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case MMU_IRQ_TAG:
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test_handler = kbase_mmu_irq_test_handler;
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rawstat_offset = MMU_REG(MMU_IRQ_RAWSTAT);
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mask_offset = MMU_REG(MMU_IRQ_MASK);
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break;
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case GPU_IRQ_TAG:
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/* already tested by pm_driver - bail out */
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default:
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return 0;
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}
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/* store old mask */
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old_mask_val = kbase_reg_read(kbdev, mask_offset, NULL);
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/* mask interrupts */
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kbase_reg_write(kbdev, mask_offset, 0x0, NULL);
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if (kbdev->irqs[tag].irq) {
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/* release original handler and install test handler */
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if (kbase_set_custom_irq_handler(kbdev, test_handler, tag) != 0) {
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err = -EINVAL;
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} else {
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kbasep_irq_test_data.timeout = 0;
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hrtimer_init(&kbasep_irq_test_data.timer,
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CLOCK_MONOTONIC, HRTIMER_MODE_REL);
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kbasep_irq_test_data.timer.function =
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kbasep_test_interrupt_timeout;
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/* trigger interrupt */
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kbase_reg_write(kbdev, mask_offset, 0x1, NULL);
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kbase_reg_write(kbdev, rawstat_offset, 0x1, NULL);
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hrtimer_start(&kbasep_irq_test_data.timer,
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HR_TIMER_DELAY_MSEC(IRQ_TEST_TIMEOUT),
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HRTIMER_MODE_REL);
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wait_event(kbasep_irq_test_data.wait,
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kbasep_irq_test_data.triggered != 0);
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if (kbasep_irq_test_data.timeout != 0) {
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dev_err(kbdev->dev, "Interrupt %d (index %d) didn't reach CPU.\n",
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kbdev->irqs[tag].irq, tag);
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err = -EINVAL;
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} else {
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dev_dbg(kbdev->dev, "Interrupt %d (index %d) reached CPU.\n",
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kbdev->irqs[tag].irq, tag);
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}
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hrtimer_cancel(&kbasep_irq_test_data.timer);
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kbasep_irq_test_data.triggered = 0;
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/* mask interrupts */
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kbase_reg_write(kbdev, mask_offset, 0x0, NULL);
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/* release test handler */
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free_irq(kbdev->irqs[tag].irq, kbase_tag(kbdev, tag));
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}
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/* restore original interrupt */
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if (request_irq(kbdev->irqs[tag].irq, kbase_handler_table[tag],
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kbdev->irqs[tag].flags | IRQF_SHARED,
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dev_name(kbdev->dev), kbase_tag(kbdev, tag))) {
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dev_err(kbdev->dev, "Can't restore original interrupt %d (index %d)\n",
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kbdev->irqs[tag].irq, tag);
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err = -EINVAL;
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}
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}
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/* restore old mask */
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kbase_reg_write(kbdev, mask_offset, old_mask_val, NULL);
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return err;
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}
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int kbasep_common_test_interrupt_handlers(
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struct kbase_device * const kbdev)
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{
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int err;
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init_waitqueue_head(&kbasep_irq_test_data.wait);
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kbasep_irq_test_data.triggered = 0;
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/* A suspend won't happen during startup/insmod */
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kbase_pm_context_active(kbdev);
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err = kbasep_common_test_interrupt(kbdev, JOB_IRQ_TAG);
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if (err) {
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dev_err(kbdev->dev, "Interrupt JOB_IRQ didn't reach CPU. Check interrupt assignments.\n");
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goto out;
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}
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err = kbasep_common_test_interrupt(kbdev, MMU_IRQ_TAG);
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if (err) {
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dev_err(kbdev->dev, "Interrupt MMU_IRQ didn't reach CPU. Check interrupt assignments.\n");
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goto out;
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}
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dev_dbg(kbdev->dev, "Interrupts are correctly assigned.\n");
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out:
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kbase_pm_context_idle(kbdev);
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return err;
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}
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#endif /* CONFIG_MALI_DEBUG */
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int kbase_install_interrupts(struct kbase_device *kbdev)
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{
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u32 nr = ARRAY_SIZE(kbase_handler_table);
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int err;
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u32 i;
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for (i = 0; i < nr; i++) {
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err = request_irq(kbdev->irqs[i].irq, kbase_handler_table[i],
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kbdev->irqs[i].flags | IRQF_SHARED,
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dev_name(kbdev->dev),
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kbase_tag(kbdev, i));
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if (err) {
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dev_err(kbdev->dev, "Can't request interrupt %d (index %d)\n",
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kbdev->irqs[i].irq, i);
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#ifdef CONFIG_SPARSE_IRQ
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dev_err(kbdev->dev, "You have CONFIG_SPARSE_IRQ support enabled - is the interrupt number correct for this configuration?\n");
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#endif /* CONFIG_SPARSE_IRQ */
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goto release;
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}
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}
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return 0;
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release:
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while (i-- > 0)
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free_irq(kbdev->irqs[i].irq, kbase_tag(kbdev, i));
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return err;
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}
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void kbase_release_interrupts(struct kbase_device *kbdev)
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{
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u32 nr = ARRAY_SIZE(kbase_handler_table);
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u32 i;
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for (i = 0; i < nr; i++) {
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if (kbdev->irqs[i].irq)
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free_irq(kbdev->irqs[i].irq, kbase_tag(kbdev, i));
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}
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}
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void kbase_synchronize_irqs(struct kbase_device *kbdev)
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{
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u32 nr = ARRAY_SIZE(kbase_handler_table);
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u32 i;
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for (i = 0; i < nr; i++) {
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if (kbdev->irqs[i].irq)
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synchronize_irq(kbdev->irqs[i].irq);
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}
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}
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#endif /* !defined(CONFIG_MALI_NO_MALI) */
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