/*
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*
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* (C) COPYRIGHT 2014 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU licence.
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*
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* A copy of the licence is included with the program, and can also be obtained
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* from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA.
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*
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*/
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/*
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* Backend-specific HW access device APIs
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*/
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#ifndef _KBASE_DEVICE_INTERNAL_H_
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#define _KBASE_DEVICE_INTERNAL_H_
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/**
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* kbase_reg_write - write to GPU register
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* @kbdev: Kbase device pointer
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* @offset: Offset of register
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* @value: Value to write
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* @kctx: Kbase context pointer. May be NULL
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*
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* Caller must ensure the GPU is powered (@kbdev->pm.gpu_powered != false). If
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* @kctx is not NULL then the caller must ensure it is scheduled (@kctx->as_nr
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* != KBASEP_AS_NR_INVALID).
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*/
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void kbase_reg_write(struct kbase_device *kbdev, u16 offset, u32 value,
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struct kbase_context *kctx);
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/**
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* kbase_reg_read - read from GPU register
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* @kbdev: Kbase device pointer
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* @offset: Offset of register
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* @kctx: Kbase context pointer. May be NULL
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*
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* Caller must ensure the GPU is powered (@kbdev->pm.gpu_powered != false). If
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* @kctx is not NULL then the caller must ensure it is scheduled (@kctx->as_nr
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* != KBASEP_AS_NR_INVALID).
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*
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* Return: Value in desired register
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*/
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u32 kbase_reg_read(struct kbase_device *kbdev, u16 offset,
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struct kbase_context *kctx);
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/**
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* kbase_gpu_interrupt - GPU interrupt handler
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* @kbdev: Kbase device pointer
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* @val: The value of the GPU IRQ status register which triggered the call
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*
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* This function is called from the interrupt handler when a GPU irq is to be
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* handled.
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*/
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void kbase_gpu_interrupt(struct kbase_device *kbdev, u32 val);
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#endif /* _KBASE_DEVICE_INTERNAL_H_ */
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