/*
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*
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* (C) COPYRIGHT 2012-2015 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU licence.
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*
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* A copy of the licence is included with the program, and can also be obtained
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* from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA.
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*
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*/
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#include <mali_kbase.h>
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#include <backend/gpu/mali_kbase_device_internal.h>
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#include "mali_kbase_debug_job_fault.h"
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#ifdef CONFIG_DEBUG_FS
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/*GPU_CONTROL_REG(r)*/
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static int gpu_control_reg_snapshot[] = {
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GPU_ID,
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SHADER_READY_LO,
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SHADER_READY_HI,
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TILER_READY_LO,
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TILER_READY_HI,
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L2_READY_LO,
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L2_READY_HI
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};
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/* JOB_CONTROL_REG(r) */
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static int job_control_reg_snapshot[] = {
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JOB_IRQ_MASK,
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JOB_IRQ_STATUS
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};
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/* JOB_SLOT_REG(n,r) */
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static int job_slot_reg_snapshot[] = {
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JS_HEAD_LO,
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JS_HEAD_HI,
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JS_TAIL_LO,
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JS_TAIL_HI,
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JS_AFFINITY_LO,
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JS_AFFINITY_HI,
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JS_CONFIG,
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JS_STATUS,
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JS_HEAD_NEXT_LO,
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JS_HEAD_NEXT_HI,
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JS_AFFINITY_NEXT_LO,
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JS_AFFINITY_NEXT_HI,
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JS_CONFIG_NEXT
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};
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/*MMU_REG(r)*/
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static int mmu_reg_snapshot[] = {
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MMU_IRQ_MASK,
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MMU_IRQ_STATUS
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};
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/* MMU_AS_REG(n,r) */
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static int as_reg_snapshot[] = {
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AS_TRANSTAB_LO,
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AS_TRANSTAB_HI,
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AS_MEMATTR_LO,
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AS_MEMATTR_HI,
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AS_FAULTSTATUS,
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AS_FAULTADDRESS_LO,
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AS_FAULTADDRESS_HI,
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AS_STATUS
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};
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bool kbase_debug_job_fault_reg_snapshot_init(struct kbase_context *kctx,
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int reg_range)
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{
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int i, j;
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int offset = 0;
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int slot_number;
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int as_number;
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if (kctx->reg_dump == NULL)
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return false;
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slot_number = kctx->kbdev->gpu_props.num_job_slots;
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as_number = kctx->kbdev->gpu_props.num_address_spaces;
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/* get the GPU control registers*/
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for (i = 0; i < sizeof(gpu_control_reg_snapshot)/4; i++) {
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kctx->reg_dump[offset] =
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GPU_CONTROL_REG(gpu_control_reg_snapshot[i]);
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offset += 2;
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}
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/* get the Job control registers*/
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for (i = 0; i < sizeof(job_control_reg_snapshot)/4; i++) {
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kctx->reg_dump[offset] =
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JOB_CONTROL_REG(job_control_reg_snapshot[i]);
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offset += 2;
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}
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/* get the Job Slot registers*/
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for (j = 0; j < slot_number; j++) {
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for (i = 0; i < sizeof(job_slot_reg_snapshot)/4; i++) {
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kctx->reg_dump[offset] =
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JOB_SLOT_REG(j, job_slot_reg_snapshot[i]);
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offset += 2;
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}
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}
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/* get the MMU registers*/
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for (i = 0; i < sizeof(mmu_reg_snapshot)/4; i++) {
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kctx->reg_dump[offset] = MMU_REG(mmu_reg_snapshot[i]);
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offset += 2;
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}
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/* get the Address space registers*/
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for (j = 0; j < as_number; j++) {
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for (i = 0; i < sizeof(as_reg_snapshot)/4; i++) {
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kctx->reg_dump[offset] =
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MMU_AS_REG(j, as_reg_snapshot[i]);
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offset += 2;
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}
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}
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WARN_ON(offset >= (reg_range*2/4));
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/* set the termination flag*/
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kctx->reg_dump[offset] = REGISTER_DUMP_TERMINATION_FLAG;
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kctx->reg_dump[offset + 1] = REGISTER_DUMP_TERMINATION_FLAG;
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dev_dbg(kctx->kbdev->dev, "kbase_job_fault_reg_snapshot_init:%d\n",
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offset);
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return true;
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}
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bool kbase_job_fault_get_reg_snapshot(struct kbase_context *kctx)
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{
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int offset = 0;
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if (kctx->reg_dump == NULL)
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return false;
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while (kctx->reg_dump[offset] != REGISTER_DUMP_TERMINATION_FLAG) {
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kctx->reg_dump[offset+1] =
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kbase_reg_read(kctx->kbdev,
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kctx->reg_dump[offset], NULL);
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offset += 2;
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}
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return true;
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}
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#endif
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