/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright 2009-2010, 2012 Freescale Semiconductor, Inc
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*
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* QorIQ based Cache Controller Memory Mapped Registers
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*
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* Author: Vivek Mahajan <vivek.mahajan@freescale.com>
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*/
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#ifndef __FSL_85XX_CACHE_CTLR_H__
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#define __FSL_85XX_CACHE_CTLR_H__
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#define L2CR_L2FI 0x40000000 /* L2 flash invalidate */
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#define L2CR_L2IO 0x00200000 /* L2 instruction only */
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#define L2CR_SRAM_ZERO 0x00000000 /* L2SRAM zero size */
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#define L2CR_SRAM_FULL 0x00010000 /* L2SRAM full size */
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#define L2CR_SRAM_HALF 0x00020000 /* L2SRAM half size */
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#define L2CR_SRAM_TWO_HALFS 0x00030000 /* L2SRAM two half sizes */
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#define L2CR_SRAM_QUART 0x00040000 /* L2SRAM one quarter size */
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#define L2CR_SRAM_TWO_QUARTS 0x00050000 /* L2SRAM two quarter size */
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#define L2CR_SRAM_EIGHTH 0x00060000 /* L2SRAM one eighth size */
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#define L2CR_SRAM_TWO_EIGHTH 0x00070000 /* L2SRAM two eighth size */
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#define L2SRAM_OPTIMAL_SZ_SHIFT 0x00000003 /* Optimum size for L2SRAM */
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#define L2SRAM_BAR_MSK_LO18 0xFFFFC000 /* Lower 18 bits */
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#define L2SRAM_BARE_MSK_HI4 0x0000000F /* Upper 4 bits */
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enum cache_sram_lock_ways {
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LOCK_WAYS_ZERO,
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LOCK_WAYS_EIGHTH,
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LOCK_WAYS_TWO_EIGHTH,
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LOCK_WAYS_HALF = 4,
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LOCK_WAYS_FULL = 8,
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};
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struct mpc85xx_l2ctlr {
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u32 ctl; /* 0x000 - L2 control */
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u8 res1[0xC];
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u32 ewar0; /* 0x010 - External write address 0 */
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u32 ewarea0; /* 0x014 - External write address extended 0 */
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u32 ewcr0; /* 0x018 - External write ctrl */
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u8 res2[4];
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u32 ewar1; /* 0x020 - External write address 1 */
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u32 ewarea1; /* 0x024 - External write address extended 1 */
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u32 ewcr1; /* 0x028 - External write ctrl 1 */
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u8 res3[4];
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u32 ewar2; /* 0x030 - External write address 2 */
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u32 ewarea2; /* 0x034 - External write address extended 2 */
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u32 ewcr2; /* 0x038 - External write ctrl 2 */
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u8 res4[4];
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u32 ewar3; /* 0x040 - External write address 3 */
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u32 ewarea3; /* 0x044 - External write address extended 3 */
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u32 ewcr3; /* 0x048 - External write ctrl 3 */
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u8 res5[0xB4];
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u32 srbar0; /* 0x100 - SRAM base address 0 */
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u32 srbarea0; /* 0x104 - SRAM base addr reg ext address 0 */
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u32 srbar1; /* 0x108 - SRAM base address 1 */
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u32 srbarea1; /* 0x10C - SRAM base addr reg ext address 1 */
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u8 res6[0xCF0];
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u32 errinjhi; /* 0xE00 - Error injection mask high */
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u32 errinjlo; /* 0xE04 - Error injection mask low */
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u32 errinjctl; /* 0xE08 - Error injection tag/ecc control */
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u8 res7[0x14];
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u32 captdatahi; /* 0xE20 - Error data high capture */
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u32 captdatalo; /* 0xE24 - Error data low capture */
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u32 captecc; /* 0xE28 - Error syndrome */
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u8 res8[0x14];
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u32 errdet; /* 0xE40 - Error detect */
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u32 errdis; /* 0xE44 - Error disable */
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u32 errinten; /* 0xE48 - Error interrupt enable */
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u32 errattr; /* 0xE4c - Error attribute capture */
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u32 erradrrl; /* 0xE50 - Error address capture low */
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u32 erradrrh; /* 0xE54 - Error address capture high */
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u32 errctl; /* 0xE58 - Error control */
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u8 res9[0x1A4];
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};
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struct sram_parameters {
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unsigned int sram_size;
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phys_addr_t sram_offset;
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};
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extern int instantiate_cache_sram(struct platform_device *dev,
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struct sram_parameters sram_params);
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extern void remove_cache_sram(struct platform_device *dev);
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#endif /* __FSL_85XX_CACHE_CTLR_H__ */
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