// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
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*/
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#include <linux/io.h>
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#include "rkpm_helpers.h"
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#include "rockchip_hptimer.h"
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/* hp timer regs */
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#define TIMER_HP_REVISION 0x0
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#define TIMER_HP_CTRL 0x4
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#define TIMER_HP_INT_EN 0x8
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#define TIMER_HP_T24_GCD 0xc
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#define TIMER_HP_T32_GCD 0x10
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#define TIMER_HP_LOAD_COUNT0 0x14
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#define TIMER_HP_LOAD_COUNT1 0x18
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#define TIMER_HP_T24_DELAT_COUNT0 0x1c
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#define TIMER_HP_T24_DELAT_COUNT1 0x20
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#define TIMER_HP_CURR_32K_VALUE0 0x24
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#define TIMER_HP_CURR_32K_VALUE1 0x28
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#define TIMER_HP_CURR_TIMER_VALUE0 0x2c
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#define TIMER_HP_CURR_TIMER_VALUE1 0x30
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#define TIMER_HP_T24_32BEGIN0 0x34
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#define TIMER_HP_T24_32BEGIN1 0x38
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#define TIMER_HP_T32_24END0 0x3c
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#define TIMER_HP_T32_24END1 0x40
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#define TIMER_HP_BEGIN_END_VALID 0x44
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#define TIMER_HP_SYNC_REQ 0x48
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#define TIMER_HP_INTR_STATUS 0x4c
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/* hptimer ctlr */
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enum rk_hptimer_ctlr_reg {
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RK_HPTIMER_CTRL_EN = 0,
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RK_HPTIMER_CTRL_MODE = 1,
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RK_HPTIMER_CTRL_CNT_MODE = 3,
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};
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/* hptimer int */
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enum rk_hptimer_int_id_t {
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RK_HPTIMER_INT_REACH = 0,
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RK_HPTIMER_INT_ADJ_DONE = 1,
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RK_HPTIMER_INT_SYNC = 2,
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};
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#define T24M_GCD 0xb71b
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#define T32K_GCD 0x40
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#define HPTIMER_WAIT_MAX_US 1000000
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static void rk_hptimer_clear_int_st(void __iomem *base, enum rk_hptimer_int_id_t id)
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{
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writel_relaxed(BIT(id), base + TIMER_HP_INTR_STATUS);
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}
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static int rk_hptimer_wait_int_st(void __iomem *base,
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enum rk_hptimer_int_id_t id,
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u64 wait_us)
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{
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while (!(readl_relaxed(base + TIMER_HP_INTR_STATUS) & BIT(id)) &&
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--wait_us > 0)
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rkpm_raw_udelay(1);
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dsb();
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if (wait_us == 0) {
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rkpm_printstr("can't wait hptimer int:");
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rkpm_printdec(id);
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rkpm_printch('-');
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rkpm_printhex(readl_relaxed(base + TIMER_HP_INTR_STATUS));
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rkpm_printch('\n');
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return -1;
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} else {
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return 0;
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}
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}
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static int rk_hptimer_wait_begin_end_valid(void __iomem *base, u64 wait_us)
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{
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while ((readl_relaxed(base + TIMER_HP_BEGIN_END_VALID) & 0x3) != 0x3 &&
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--wait_us > 0)
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rkpm_raw_udelay(1);
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dsb();
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if (wait_us == 0) {
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rkpm_printstr("can't wait hptimer begin_end valid:");
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rkpm_printhex(readl_relaxed(base + TIMER_HP_BEGIN_END_VALID));
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rkpm_printch('\n');
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return -1;
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} else {
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return 0;
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}
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}
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static u64 rk_hptimer_get_soft_adjust_delt_cnt(void __iomem *base)
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{
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u64 begin, end, delt;
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if (rk_hptimer_wait_begin_end_valid(base, HPTIMER_WAIT_MAX_US))
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return 0;
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begin = (u64)readl_relaxed(base + TIMER_HP_T24_32BEGIN0) |
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(u64)readl_relaxed(base + TIMER_HP_T24_32BEGIN1) << 32;
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end = (u64)readl_relaxed(base + TIMER_HP_T32_24END0) |
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(u64)readl_relaxed(base + TIMER_HP_T32_24END1) << 32;
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delt = (end - begin) * T24M_GCD / T32K_GCD;
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writel_relaxed(0x3, base + TIMER_HP_BEGIN_END_VALID);
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return delt;
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}
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static void rk_hptimer_soft_adjust_req(void __iomem *base, u64 delt)
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{
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if (delt == 0)
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return;
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writel_relaxed(delt & 0xffffffff, base + TIMER_HP_T24_DELAT_COUNT0);
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writel_relaxed((delt >> 32) & 0xffffffff, base + TIMER_HP_T24_DELAT_COUNT1);
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dsb();
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writel_relaxed(0x1, base + TIMER_HP_SYNC_REQ);
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dsb();
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}
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int rk_hptimer_is_enabled(void __iomem *base)
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{
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return !!(readl_relaxed(base + TIMER_HP_CTRL) & BIT(RK_HPTIMER_CTRL_EN));
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}
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int rk_hptimer_get_mode(void __iomem *base)
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{
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return (readl_relaxed(base + TIMER_HP_CTRL) >> RK_HPTIMER_CTRL_MODE) & 0x3;
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}
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u64 rk_hptimer_get_count(void __iomem *base)
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{
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u64 cnt;
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cnt = (u64)readl_relaxed(base + TIMER_HP_CURR_TIMER_VALUE0) |
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(u64)readl_relaxed(base + TIMER_HP_CURR_TIMER_VALUE1) << 32;
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return cnt;
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}
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int rk_hptimer_wait_mode(void __iomem *base, enum rk_hptimer_mode_t mode)
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{
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if (mode == RK_HPTIMER_NORM_MODE)
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return 0;
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if (mode == RK_HPTIMER_HARD_ADJUST_MODE) {
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/* wait adjust done if hard_adjust_mode */
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if (rk_hptimer_wait_int_st(base, RK_HPTIMER_INT_ADJ_DONE,
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HPTIMER_WAIT_MAX_US))
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return -1;
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rk_hptimer_clear_int_st(base, RK_HPTIMER_INT_ADJ_DONE);
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} else if (mode == RK_HPTIMER_SOFT_ADJUST_MODE) {
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/* wait 32k sync done */
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if (rk_hptimer_wait_int_st(base, RK_HPTIMER_INT_SYNC,
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HPTIMER_WAIT_MAX_US))
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return -1;
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rk_hptimer_clear_int_st(base, RK_HPTIMER_INT_SYNC);
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}
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return 0;
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}
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void rk_hptimer_do_soft_adjust(void __iomem *base)
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{
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u64 delt = rk_hptimer_get_soft_adjust_delt_cnt(base);
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rk_hptimer_soft_adjust_req(base, delt);
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rk_hptimer_wait_mode(base, RK_HPTIMER_SOFT_ADJUST_MODE);
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}
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void rk_hptimer_do_soft_adjust_no_wait(void __iomem *base)
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{
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u64 delt = rk_hptimer_get_soft_adjust_delt_cnt(base);
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rk_hptimer_soft_adjust_req(base, delt);
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}
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void rk_hptimer_mode_init(void __iomem *base, enum rk_hptimer_mode_t mode)
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{
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u64 old_cnt = rk_hptimer_get_count(base);
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u32 val;
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writel_relaxed(0x0, base + TIMER_HP_CTRL);
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writel_relaxed(0x0, base + TIMER_HP_INT_EN);
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writel_relaxed(0x7, base + TIMER_HP_INTR_STATUS);
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writel_relaxed(0x3, base + TIMER_HP_BEGIN_END_VALID);
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writel_relaxed(0xffffffff, base + TIMER_HP_LOAD_COUNT0);
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writel_relaxed(0xffffffff, base + TIMER_HP_LOAD_COUNT1);
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/* config T24/T32 GCD if hard_adjust_mode */
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if (mode == RK_HPTIMER_HARD_ADJUST_MODE) {
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writel_relaxed(T24M_GCD, base + TIMER_HP_T24_GCD);
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writel_relaxed(T32K_GCD, base + TIMER_HP_T32_GCD);
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}
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dsb();
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if (mode != RK_HPTIMER_NORM_MODE) {
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writel_relaxed(0x7, base + TIMER_HP_INT_EN);
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writel_relaxed(mode << RK_HPTIMER_CTRL_MODE, base + TIMER_HP_CTRL);
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dsb();
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}
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val = readl_relaxed(base + TIMER_HP_CTRL);
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writel_relaxed(val | BIT(RK_HPTIMER_CTRL_EN), base + TIMER_HP_CTRL);
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dsb();
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/* compensate old_cnt to hptimer if soft_adjust_mode */
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if (mode == RK_HPTIMER_SOFT_ADJUST_MODE)
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rk_hptimer_soft_adjust_req(base, old_cnt);
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if (rk_hptimer_wait_mode(base, mode))
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pr_err("%s: can't wait hptimer mode:%d\n", __func__, mode);
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}
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