/*
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* Copyright (C) 2014 Marvell
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*
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#define pr_fmt(fmt) "mvebu-cpureset: " fmt
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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#include <linux/resource.h>
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#include "common.h"
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static void __iomem *cpu_reset_base;
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static size_t cpu_reset_size;
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#define CPU_RESET_OFFSET(cpu) (cpu * 0x8)
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#define CPU_RESET_ASSERT BIT(0)
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int mvebu_cpu_reset_deassert(int cpu)
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{
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u32 reg;
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if (!cpu_reset_base)
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return -ENODEV;
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if (CPU_RESET_OFFSET(cpu) >= cpu_reset_size)
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return -EINVAL;
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reg = readl(cpu_reset_base + CPU_RESET_OFFSET(cpu));
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reg &= ~CPU_RESET_ASSERT;
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writel(reg, cpu_reset_base + CPU_RESET_OFFSET(cpu));
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return 0;
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}
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static int mvebu_cpu_reset_map(struct device_node *np, int res_idx)
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{
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struct resource res;
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if (of_address_to_resource(np, res_idx, &res)) {
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pr_err("unable to get resource\n");
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return -ENOENT;
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}
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if (!request_mem_region(res.start, resource_size(&res),
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np->full_name)) {
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pr_err("unable to request region\n");
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return -EBUSY;
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}
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cpu_reset_base = ioremap(res.start, resource_size(&res));
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if (!cpu_reset_base) {
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pr_err("unable to map registers\n");
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release_mem_region(res.start, resource_size(&res));
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return -ENOMEM;
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}
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cpu_reset_size = resource_size(&res);
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return 0;
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}
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static int __init mvebu_cpu_reset_init(void)
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{
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struct device_node *np;
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int res_idx;
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int ret;
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np = of_find_compatible_node(NULL, NULL,
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"marvell,armada-370-cpu-reset");
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if (np) {
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res_idx = 0;
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} else {
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/*
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* This code is kept for backward compatibility with
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* old Device Trees.
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*/
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np = of_find_compatible_node(NULL, NULL,
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"marvell,armada-370-xp-pmsu");
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if (np) {
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pr_warn(FW_WARN "deprecated pmsu binding\n");
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res_idx = 1;
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}
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}
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/* No reset node found */
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if (!np)
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return -ENODEV;
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ret = mvebu_cpu_reset_map(np, res_idx);
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of_node_put(np);
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return ret;
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}
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early_initcall(mvebu_cpu_reset_init);
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