/*
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* IRQ definitions for Marvell Dove 88AP510 SoC
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_IRQS_H
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#define __ASM_ARCH_IRQS_H
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/*
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* Dove Low Interrupt Controller
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*/
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#define IRQ_DOVE_BRIDGE (1 + 0)
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#define IRQ_DOVE_H2C (1 + 1)
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#define IRQ_DOVE_C2H (1 + 2)
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#define IRQ_DOVE_NAND (1 + 3)
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#define IRQ_DOVE_PDMA (1 + 4)
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#define IRQ_DOVE_SPI1 (1 + 5)
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#define IRQ_DOVE_SPI0 (1 + 6)
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#define IRQ_DOVE_UART_0 (1 + 7)
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#define IRQ_DOVE_UART_1 (1 + 8)
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#define IRQ_DOVE_UART_2 (1 + 9)
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#define IRQ_DOVE_UART_3 (1 + 10)
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#define IRQ_DOVE_I2C (1 + 11)
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#define IRQ_DOVE_GPIO_0_7 (1 + 12)
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#define IRQ_DOVE_GPIO_8_15 (1 + 13)
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#define IRQ_DOVE_GPIO_16_23 (1 + 14)
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#define IRQ_DOVE_PCIE0_ERR (1 + 15)
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#define IRQ_DOVE_PCIE0 (1 + 16)
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#define IRQ_DOVE_PCIE1_ERR (1 + 17)
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#define IRQ_DOVE_PCIE1 (1 + 18)
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#define IRQ_DOVE_I2S0 (1 + 19)
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#define IRQ_DOVE_I2S0_ERR (1 + 20)
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#define IRQ_DOVE_I2S1 (1 + 21)
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#define IRQ_DOVE_I2S1_ERR (1 + 22)
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#define IRQ_DOVE_USB_ERR (1 + 23)
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#define IRQ_DOVE_USB0 (1 + 24)
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#define IRQ_DOVE_USB1 (1 + 25)
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#define IRQ_DOVE_GE00_RX (1 + 26)
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#define IRQ_DOVE_GE00_TX (1 + 27)
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#define IRQ_DOVE_GE00_MISC (1 + 28)
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#define IRQ_DOVE_GE00_SUM (1 + 29)
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#define IRQ_DOVE_GE00_ERR (1 + 30)
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#define IRQ_DOVE_CRYPTO (1 + 31)
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/*
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* Dove High Interrupt Controller
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*/
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#define IRQ_DOVE_AC97 (1 + 32)
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#define IRQ_DOVE_PMU (1 + 33)
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#define IRQ_DOVE_CAM (1 + 34)
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#define IRQ_DOVE_SDIO0 (1 + 35)
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#define IRQ_DOVE_SDIO1 (1 + 36)
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#define IRQ_DOVE_SDIO0_WAKEUP (1 + 37)
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#define IRQ_DOVE_SDIO1_WAKEUP (1 + 38)
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#define IRQ_DOVE_XOR_00 (1 + 39)
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#define IRQ_DOVE_XOR_01 (1 + 40)
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#define IRQ_DOVE_XOR0_ERR (1 + 41)
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#define IRQ_DOVE_XOR_10 (1 + 42)
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#define IRQ_DOVE_XOR_11 (1 + 43)
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#define IRQ_DOVE_XOR1_ERR (1 + 44)
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#define IRQ_DOVE_LCD_DCON (1 + 45)
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#define IRQ_DOVE_LCD1 (1 + 46)
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#define IRQ_DOVE_LCD0 (1 + 47)
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#define IRQ_DOVE_GPU (1 + 48)
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#define IRQ_DOVE_PERFORM_MNTR (1 + 49)
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#define IRQ_DOVE_VPRO_DMA1 (1 + 51)
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#define IRQ_DOVE_SSP_TIMER (1 + 54)
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#define IRQ_DOVE_SSP (1 + 55)
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#define IRQ_DOVE_MC_L2_ERR (1 + 56)
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#define IRQ_DOVE_CRYPTO_ERR (1 + 59)
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#define IRQ_DOVE_GPIO_24_31 (1 + 60)
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#define IRQ_DOVE_HIGH_GPIO (1 + 61)
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#define IRQ_DOVE_SATA (1 + 62)
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/*
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* DOVE General Purpose Pins
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*/
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#define IRQ_DOVE_GPIO_START 65
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#define NR_GPIO_IRQS 64
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/*
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* PMU interrupts
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*/
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#define IRQ_DOVE_PMU_START (IRQ_DOVE_GPIO_START + NR_GPIO_IRQS)
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#define NR_PMU_IRQS 7
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#define IRQ_DOVE_RTC (IRQ_DOVE_PMU_START + 5)
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#define DOVE_NR_IRQS (IRQ_DOVE_PMU_START + NR_PMU_IRQS)
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#endif
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