/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* linux/arch/arm/kernel/head-nommu.S
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*
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* Copyright (C) 1994-2002 Russell King
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* Copyright (C) 2003-2006 Hyok S. Choi
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*
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* Common kernel startup code (non-paged MM)
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <asm/assembler.h>
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#include <asm/ptrace.h>
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#include <asm/asm-offsets.h>
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#include <asm/memory.h>
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#include <asm/cp15.h>
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#include <asm/thread_info.h>
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#include <asm/v7m.h>
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#include <asm/mpu.h>
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#include <asm/page.h>
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/*
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* Kernel startup entry point.
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* ---------------------------
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*
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* This is normally called from the decompressor code. The requirements
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* are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
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* r1 = machine nr.
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*
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* See linux/arch/arm/tools/mach-types for the complete list of machine
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* numbers for r1.
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*
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*/
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__HEAD
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#ifdef CONFIG_CPU_THUMBONLY
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.thumb
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ENTRY(stext)
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#else
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.arm
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ENTRY(stext)
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THUMB( badr r9, 1f ) @ Kernel is always entered in ARM.
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THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
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THUMB( .thumb ) @ switch to Thumb now.
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THUMB(1: )
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#endif
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#ifdef CONFIG_ARM_VIRT_EXT
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bl __hyp_stub_install
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#endif
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@ ensure svc mode and all interrupts masked
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safe_svcmode_maskall r9
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@ and irqs disabled
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#if defined(CONFIG_CPU_CP15)
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mrc p15, 0, r9, c0, c0 @ get processor id
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#elif defined(CONFIG_CPU_V7M)
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ldr r9, =BASEADDR_V7M_SCB
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ldr r9, [r9, V7M_SCB_CPUID]
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#else
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ldr r9, =CONFIG_PROCESSOR_ID
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#endif
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bl __lookup_processor_type @ r5=procinfo r9=cpuid
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movs r10, r5 @ invalid processor (r5=0)?
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beq __error_p @ yes, error 'p'
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#ifdef CONFIG_ARM_MPU
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bl __setup_mpu
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#endif
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badr lr, 1f @ return (PIC) address
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ldr r12, [r10, #PROCINFO_INITFUNC]
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add r12, r12, r10
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ret r12
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1: ldr lr, =__mmap_switched
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b __after_proc_init
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ENDPROC(stext)
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#ifdef CONFIG_SMP
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.text
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ENTRY(secondary_startup)
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/*
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* Common entry point for secondary CPUs.
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*
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* Ensure that we're in SVC mode, and IRQs are disabled. Lookup
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* the processor type - there is no need to check the machine type
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* as it has already been validated by the primary processor.
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*/
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#ifdef CONFIG_ARM_VIRT_EXT
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bl __hyp_stub_install_secondary
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#endif
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safe_svcmode_maskall r9
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#ifndef CONFIG_CPU_CP15
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ldr r9, =CONFIG_PROCESSOR_ID
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#else
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mrc p15, 0, r9, c0, c0 @ get processor id
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#endif
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bl __lookup_processor_type @ r5=procinfo r9=cpuid
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movs r10, r5 @ invalid processor?
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beq __error_p @ yes, error 'p'
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ldr r7, __secondary_data
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#ifdef CONFIG_ARM_MPU
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bl __secondary_setup_mpu @ Initialize the MPU
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#endif
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badr lr, 1f @ return (PIC) address
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ldr r12, [r10, #PROCINFO_INITFUNC]
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add r12, r12, r10
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ret r12
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1: bl __after_proc_init
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ldr sp, [r7, #12] @ set up the stack pointer
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mov fp, #0
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b secondary_start_kernel
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ENDPROC(secondary_startup)
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.type __secondary_data, %object
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__secondary_data:
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.long secondary_data
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#endif /* CONFIG_SMP */
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/*
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* Set the Control Register and Read the process ID.
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*/
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.text
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__after_proc_init:
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M_CLASS(movw r12, #:lower16:BASEADDR_V7M_SCB)
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M_CLASS(movt r12, #:upper16:BASEADDR_V7M_SCB)
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#ifdef CONFIG_ARM_MPU
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M_CLASS(ldr r3, [r12, 0x50])
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AR_CLASS(mrc p15, 0, r3, c0, c1, 4) @ Read ID_MMFR0
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and r3, r3, #(MMFR0_PMSA) @ PMSA field
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teq r3, #(MMFR0_PMSAv7) @ PMSA v7
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beq 1f
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teq r3, #(MMFR0_PMSAv8) @ PMSA v8
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/*
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* Memory region attributes for PMSAv8:
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*
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* n = AttrIndx[2:0]
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* n MAIR
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* DEVICE_nGnRnE 000 00000000
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* NORMAL 001 11111111
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*/
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ldreq r3, =PMSAv8_MAIR(0x00, PMSAv8_RGN_DEVICE_nGnRnE) | \
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PMSAv8_MAIR(0xff, PMSAv8_RGN_NORMAL)
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AR_CLASS(mcreq p15, 0, r3, c10, c2, 0) @ MAIR 0
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M_CLASS(streq r3, [r12, #PMSAv8_MAIR0])
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moveq r3, #0
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AR_CLASS(mcreq p15, 0, r3, c10, c2, 1) @ MAIR 1
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M_CLASS(streq r3, [r12, #PMSAv8_MAIR1])
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1:
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#endif
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#ifdef CONFIG_CPU_CP15
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/*
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* CP15 system control register value returned in r0 from
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* the CPU init function.
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*/
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#ifdef CONFIG_ARM_MPU
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biceq r0, r0, #CR_BR @ Disable the 'default mem-map'
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orreq r0, r0, #CR_M @ Set SCTRL.M (MPU on)
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#endif
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#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
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orr r0, r0, #CR_A
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#else
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bic r0, r0, #CR_A
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#endif
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#ifdef CONFIG_CPU_DCACHE_DISABLE
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bic r0, r0, #CR_C
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#endif
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#ifdef CONFIG_CPU_BPREDICT_DISABLE
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bic r0, r0, #CR_Z
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#endif
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#ifdef CONFIG_CPU_ICACHE_DISABLE
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bic r0, r0, #CR_I
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#endif
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mcr p15, 0, r0, c1, c0, 0 @ write control reg
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instr_sync
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#elif defined (CONFIG_CPU_V7M)
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#ifdef CONFIG_ARM_MPU
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ldreq r3, [r12, MPU_CTRL]
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biceq r3, #MPU_CTRL_PRIVDEFENA
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orreq r3, #MPU_CTRL_ENABLE
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streq r3, [r12, MPU_CTRL]
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isb
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#endif
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/* For V7M systems we want to modify the CCR similarly to the SCTLR */
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#ifdef CONFIG_CPU_DCACHE_DISABLE
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bic r0, r0, #V7M_SCB_CCR_DC
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#endif
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#ifdef CONFIG_CPU_BPREDICT_DISABLE
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bic r0, r0, #V7M_SCB_CCR_BP
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#endif
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#ifdef CONFIG_CPU_ICACHE_DISABLE
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bic r0, r0, #V7M_SCB_CCR_IC
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#endif
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str r0, [r12, V7M_SCB_CCR]
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/* Pass exc_ret to __mmap_switched */
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mov r0, r10
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#endif /* CONFIG_CPU_CP15 elif CONFIG_CPU_V7M */
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ret lr
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ENDPROC(__after_proc_init)
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.ltorg
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#ifdef CONFIG_ARM_MPU
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#ifndef CONFIG_CPU_V7M
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/* Set which MPU region should be programmed */
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.macro set_region_nr tmp, rgnr, unused
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mov \tmp, \rgnr @ Use static region numbers
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mcr p15, 0, \tmp, c6, c2, 0 @ Write RGNR
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.endm
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/* Setup a single MPU region, either D or I side (D-side for unified) */
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.macro setup_region bar, acr, sr, side = PMSAv7_DATA_SIDE, unused
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mcr p15, 0, \bar, c6, c1, (0 + \side) @ I/DRBAR
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mcr p15, 0, \acr, c6, c1, (4 + \side) @ I/DRACR
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mcr p15, 0, \sr, c6, c1, (2 + \side) @ I/DRSR
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.endm
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#else
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.macro set_region_nr tmp, rgnr, base
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mov \tmp, \rgnr
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str \tmp, [\base, #PMSAv7_RNR]
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.endm
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.macro setup_region bar, acr, sr, unused, base
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lsl \acr, \acr, #16
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orr \acr, \acr, \sr
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str \bar, [\base, #PMSAv7_RBAR]
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str \acr, [\base, #PMSAv7_RASR]
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.endm
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#endif
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/*
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* Setup the MPU and initial MPU Regions. We create the following regions:
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* Region 0: Use this for probing the MPU details, so leave disabled.
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* Region 1: Background region - covers the whole of RAM as strongly ordered
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* Region 2: Normal, Shared, cacheable for RAM. From PHYS_OFFSET, size from r6
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* Region 3: Normal, shared, inaccessible from PL0 to protect the vectors page
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*
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* r6: Value to be written to DRSR (and IRSR if required) for PMSAv7_RAM_REGION
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*/
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__HEAD
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ENTRY(__setup_mpu)
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/* Probe for v7 PMSA compliance */
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M_CLASS(movw r12, #:lower16:BASEADDR_V7M_SCB)
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M_CLASS(movt r12, #:upper16:BASEADDR_V7M_SCB)
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AR_CLASS(mrc p15, 0, r0, c0, c1, 4) @ Read ID_MMFR0
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M_CLASS(ldr r0, [r12, 0x50])
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and r0, r0, #(MMFR0_PMSA) @ PMSA field
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teq r0, #(MMFR0_PMSAv7) @ PMSA v7
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beq __setup_pmsa_v7
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teq r0, #(MMFR0_PMSAv8) @ PMSA v8
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beq __setup_pmsa_v8
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ret lr
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ENDPROC(__setup_mpu)
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ENTRY(__setup_pmsa_v7)
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/* Calculate the size of a region covering just the kernel */
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ldr r5, =PLAT_PHYS_OFFSET @ Region start: PHYS_OFFSET
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ldr r6, =(_end) @ Cover whole kernel
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sub r6, r6, r5 @ Minimum size of region to map
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clz r6, r6 @ Region size must be 2^N...
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rsb r6, r6, #31 @ ...so round up region size
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lsl r6, r6, #PMSAv7_RSR_SZ @ Put size in right field
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orr r6, r6, #(1 << PMSAv7_RSR_EN) @ Set region enabled bit
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/* Determine whether the D/I-side memory map is unified. We set the
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* flags here and continue to use them for the rest of this function */
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AR_CLASS(mrc p15, 0, r0, c0, c0, 4) @ MPUIR
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M_CLASS(ldr r0, [r12, #MPU_TYPE])
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ands r5, r0, #MPUIR_DREGION_SZMASK @ 0 size d region => No MPU
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bxeq lr
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tst r0, #MPUIR_nU @ MPUIR_nU = 0 for unified
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/* Setup second region first to free up r6 */
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set_region_nr r0, #PMSAv7_RAM_REGION, r12
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isb
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/* Full access from PL0, PL1, shared for CONFIG_SMP, cacheable */
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ldr r0, =PLAT_PHYS_OFFSET @ RAM starts at PHYS_OFFSET
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ldr r5,=(PMSAv7_AP_PL1RW_PL0RW | PMSAv7_RGN_NORMAL)
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setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ PHYS_OFFSET, shared, enabled
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beq 1f @ Memory-map not unified
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setup_region r0, r5, r6, PMSAv7_INSTR_SIDE, r12 @ PHYS_OFFSET, shared, enabled
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1: isb
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/* First/background region */
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set_region_nr r0, #PMSAv7_BG_REGION, r12
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isb
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/* Execute Never, strongly ordered, inaccessible to PL0, rw PL1 */
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mov r0, #0 @ BG region starts at 0x0
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ldr r5,=(PMSAv7_ACR_XN | PMSAv7_RGN_STRONGLY_ORDERED | PMSAv7_AP_PL1RW_PL0NA)
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mov r6, #PMSAv7_RSR_ALL_MEM @ 4GB region, enabled
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setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ 0x0, BG region, enabled
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beq 2f @ Memory-map not unified
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setup_region r0, r5, r6, PMSAv7_INSTR_SIDE r12 @ 0x0, BG region, enabled
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2: isb
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#ifdef CONFIG_XIP_KERNEL
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set_region_nr r0, #PMSAv7_ROM_REGION, r12
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isb
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ldr r5,=(PMSAv7_AP_PL1RO_PL0NA | PMSAv7_RGN_NORMAL)
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ldr r0, =CONFIG_XIP_PHYS_ADDR @ ROM start
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ldr r6, =(_exiprom) @ ROM end
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sub r6, r6, r0 @ Minimum size of region to map
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clz r6, r6 @ Region size must be 2^N...
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rsb r6, r6, #31 @ ...so round up region size
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lsl r6, r6, #PMSAv7_RSR_SZ @ Put size in right field
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orr r6, r6, #(1 << PMSAv7_RSR_EN) @ Set region enabled bit
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setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ XIP_PHYS_ADDR, shared, enabled
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beq 3f @ Memory-map not unified
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setup_region r0, r5, r6, PMSAv7_INSTR_SIDE, r12 @ XIP_PHYS_ADDR, shared, enabled
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3: isb
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#endif
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ret lr
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ENDPROC(__setup_pmsa_v7)
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ENTRY(__setup_pmsa_v8)
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mov r0, #0
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AR_CLASS(mcr p15, 0, r0, c6, c2, 1) @ PRSEL
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M_CLASS(str r0, [r12, #PMSAv8_RNR])
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isb
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#ifdef CONFIG_XIP_KERNEL
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ldr r5, =CONFIG_XIP_PHYS_ADDR @ ROM start
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ldr r6, =(_exiprom) @ ROM end
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sub r6, r6, #1
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bic r6, r6, #(PMSAv8_MINALIGN - 1)
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orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED)
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orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_NORMAL) | PMSAv8_LAR_EN)
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AR_CLASS(mcr p15, 0, r5, c6, c8, 0) @ PRBAR0
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AR_CLASS(mcr p15, 0, r6, c6, c8, 1) @ PRLAR0
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M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(0)])
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M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(0)])
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#endif
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ldr r5, =KERNEL_START
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ldr r6, =KERNEL_END
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sub r6, r6, #1
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bic r6, r6, #(PMSAv8_MINALIGN - 1)
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orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED)
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orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_NORMAL) | PMSAv8_LAR_EN)
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AR_CLASS(mcr p15, 0, r5, c6, c8, 4) @ PRBAR1
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AR_CLASS(mcr p15, 0, r6, c6, c8, 5) @ PRLAR1
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M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(1)])
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M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(1)])
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/* Setup Background: 0x0 - min(KERNEL_START, XIP_PHYS_ADDR) */
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#ifdef CONFIG_XIP_KERNEL
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ldr r6, =KERNEL_START
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ldr r5, =CONFIG_XIP_PHYS_ADDR
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cmp r6, r5
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movcs r6, r5
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#else
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ldr r6, =KERNEL_START
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#endif
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cmp r6, #0
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beq 1f
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mov r5, #0
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sub r6, r6, #1
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bic r6, r6, #(PMSAv8_MINALIGN - 1)
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orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED | PMSAv8_BAR_XN)
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orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN)
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AR_CLASS(mcr p15, 0, r5, c6, c9, 0) @ PRBAR2
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AR_CLASS(mcr p15, 0, r6, c6, c9, 1) @ PRLAR2
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M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(2)])
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M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(2)])
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1:
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/* Setup Background: max(KERNEL_END, _exiprom) - 0xffffffff */
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#ifdef CONFIG_XIP_KERNEL
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ldr r5, =KERNEL_END
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ldr r6, =(_exiprom)
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cmp r5, r6
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movcc r5, r6
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#else
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ldr r5, =KERNEL_END
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#endif
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mov r6, #0xffffffff
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bic r6, r6, #(PMSAv8_MINALIGN - 1)
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orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED | PMSAv8_BAR_XN)
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orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN)
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AR_CLASS(mcr p15, 0, r5, c6, c9, 4) @ PRBAR3
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AR_CLASS(mcr p15, 0, r6, c6, c9, 5) @ PRLAR3
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M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(3)])
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M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(3)])
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#ifdef CONFIG_XIP_KERNEL
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/* Setup Background: min(_exiprom, KERNEL_END) - max(KERNEL_START, XIP_PHYS_ADDR) */
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ldr r5, =(_exiprom)
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ldr r6, =KERNEL_END
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cmp r5, r6
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movcs r5, r6
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ldr r6, =KERNEL_START
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ldr r0, =CONFIG_XIP_PHYS_ADDR
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cmp r6, r0
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movcc r6, r0
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sub r6, r6, #1
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bic r6, r6, #(PMSAv8_MINALIGN - 1)
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orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED | PMSAv8_BAR_XN)
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orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN)
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#ifdef CONFIG_CPU_V7M
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/* There is no alias for n == 4 */
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mov r0, #4
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str r0, [r12, #PMSAv8_RNR] @ PRSEL
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isb
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str r5, [r12, #PMSAv8_RBAR_A(0)]
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str r6, [r12, #PMSAv8_RLAR_A(0)]
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#else
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mcr p15, 0, r5, c6, c10, 0 @ PRBAR4
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mcr p15, 0, r6, c6, c10, 1 @ PRLAR4
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#endif
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#endif
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ret lr
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ENDPROC(__setup_pmsa_v8)
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#ifdef CONFIG_SMP
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/*
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* r6: pointer at mpu_rgn_info
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*/
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.text
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ENTRY(__secondary_setup_mpu)
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/* Use MPU region info supplied by __cpu_up */
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ldr r6, [r7] @ get secondary_data.mpu_rgn_info
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/* Probe for v7 PMSA compliance */
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mrc p15, 0, r0, c0, c1, 4 @ Read ID_MMFR0
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and r0, r0, #(MMFR0_PMSA) @ PMSA field
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teq r0, #(MMFR0_PMSAv7) @ PMSA v7
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beq __secondary_setup_pmsa_v7
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teq r0, #(MMFR0_PMSAv8) @ PMSA v8
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beq __secondary_setup_pmsa_v8
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b __error_p
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ENDPROC(__secondary_setup_mpu)
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/*
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* r6: pointer at mpu_rgn_info
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*/
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ENTRY(__secondary_setup_pmsa_v7)
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/* Determine whether the D/I-side memory map is unified. We set the
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* flags here and continue to use them for the rest of this function */
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mrc p15, 0, r0, c0, c0, 4 @ MPUIR
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ands r5, r0, #MPUIR_DREGION_SZMASK @ 0 size d region => No MPU
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beq __error_p
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ldr r4, [r6, #MPU_RNG_INFO_USED]
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mov r5, #MPU_RNG_SIZE
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add r3, r6, #MPU_RNG_INFO_RNGS
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mla r3, r4, r5, r3
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1:
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tst r0, #MPUIR_nU @ MPUIR_nU = 0 for unified
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sub r3, r3, #MPU_RNG_SIZE
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sub r4, r4, #1
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set_region_nr r0, r4
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isb
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ldr r0, [r3, #MPU_RGN_DRBAR]
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ldr r6, [r3, #MPU_RGN_DRSR]
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ldr r5, [r3, #MPU_RGN_DRACR]
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setup_region r0, r5, r6, PMSAv7_DATA_SIDE
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beq 2f
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setup_region r0, r5, r6, PMSAv7_INSTR_SIDE
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2: isb
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mrc p15, 0, r0, c0, c0, 4 @ Reevaluate the MPUIR
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cmp r4, #0
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bgt 1b
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ret lr
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ENDPROC(__secondary_setup_pmsa_v7)
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|
ENTRY(__secondary_setup_pmsa_v8)
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ldr r4, [r6, #MPU_RNG_INFO_USED]
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#ifndef CONFIG_XIP_KERNEL
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add r4, r4, #1
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#endif
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mov r5, #MPU_RNG_SIZE
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add r3, r6, #MPU_RNG_INFO_RNGS
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mla r3, r4, r5, r3
|
|
1:
|
sub r3, r3, #MPU_RNG_SIZE
|
sub r4, r4, #1
|
|
mcr p15, 0, r4, c6, c2, 1 @ PRSEL
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isb
|
|
ldr r5, [r3, #MPU_RGN_PRBAR]
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ldr r6, [r3, #MPU_RGN_PRLAR]
|
|
mcr p15, 0, r5, c6, c3, 0 @ PRBAR
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mcr p15, 0, r6, c6, c3, 1 @ PRLAR
|
|
cmp r4, #0
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bgt 1b
|
|
ret lr
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ENDPROC(__secondary_setup_pmsa_v8)
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#endif /* CONFIG_SMP */
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#endif /* CONFIG_ARM_MPU */
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#include "head-common.S"
|
