/* SPDX-License-Identifier: ((GPL-2.0+ WITH Linux-syscall-note) OR MIT)
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*
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* Copyright (C) 2019 Rockchip Electronics Co., Ltd.
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*/
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#ifndef _UAPI_RKISPP_CONFIG_H
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#define _UAPI_RKISPP_CONFIG_H
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#include <linux/types.h>
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#include <linux/v4l2-controls.h>
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#define ISPP_API_VERSION KERNEL_VERSION(1, 8, 0)
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#define ISPP_ID_TNR (0)
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#define ISPP_ID_NR (1)
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#define ISPP_ID_SHP (2)
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#define ISPP_ID_FEC (3)
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#define ISPP_ID_ORB (4)
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#define ISPP_ID_MAX (5)
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#define ISPP_MODULE_TNR BIT(ISPP_ID_TNR)//2TO1
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#define ISPP_MODULE_NR BIT(ISPP_ID_NR)
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#define ISPP_MODULE_SHP BIT(ISPP_ID_SHP)
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#define ISPP_MODULE_FEC BIT(ISPP_ID_FEC)//CALIBRATION
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#define ISPP_MODULE_ORB BIT(ISPP_ID_ORB)
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//extra function
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#define ISPP_MODULE_TNR_3TO1 (BIT(16) | ISPP_MODULE_TNR)
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#define ISPP_MODULE_FEC_ST (BIT(17) | ISPP_MODULE_FEC)//STABILIZATION
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#define TNR_SIGMA_CURVE_SIZE 17
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#define TNR_LUMA_CURVE_SIZE 6
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#define TNR_GFCOEF6_SIZE 6
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#define TNR_GFCOEF3_SIZE 3
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#define TNR_SCALE_YG_SIZE 4
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#define TNR_SCALE_YL_SIZE 3
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#define TNR_SCALE_CG_SIZE 3
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#define TNR_SCALE_Y2CG_SIZE 3
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#define TNR_SCALE_CL_SIZE 2
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#define TNR_SCALE_Y2CL_SIZE 3
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#define TNR_WEIGHT_Y_SIZE 3
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#define NR_UVNR_UVGAIN_SIZE 2
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#define NR_UVNR_T1FLT_WTQ_SIZE 8
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#define NR_UVNR_T2GEN_WTQ_SIZE 4
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#define NR_UVNR_T2FLT_WT_SIZE 3
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#define NR_YNR_SGM_DX_SIZE 16
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#define NR_YNR_SGM_Y_SIZE 17
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#define NR_YNR_HWEIT_D_SIZE 20
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#define NR_YNR_HGRAD_Y_SIZE 24
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#define NR_YNR_HSTV_Y_SIZE 17
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#define NR_YNR_CI_SIZE 4
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#define NR_YNR_LGAIN_MIN_SIZE 4
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#define NR_YNR_LWEIT_FLT_SIZE 4
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#define NR_YNR_HGAIN_SGM_SIZE 4
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#define NR_YNR_HWEIT_SIZE 4
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#define NR_YNR_LWEIT_CMP_SIZE 2
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#define NR_YNR_ST_SCALE_SIZE 3
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#define SHP_PBF_KERNEL_SIZE 3
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#define SHP_MRF_KERNEL_SIZE 6
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#define SHP_MBF_KERNEL_SIZE 12
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#define SHP_HRF_KERNEL_SIZE 6
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#define SHP_HBF_KERNEL_SIZE 3
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#define SHP_EDGE_COEF_SIZE 3
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#define SHP_EDGE_SMOTH_SIZE 3
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#define SHP_EDGE_GAUS_SIZE 6
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#define SHP_DOG_KERNEL_SIZE 6
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#define SHP_LUM_POINT_SIZE 6
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#define SHP_SIGMA_SIZE 8
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#define SHP_LUM_CLP_SIZE 8
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#define SHP_LUM_MIN_SIZE 8
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#define SHP_EDGE_LUM_THED_SIZE 8
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#define SHP_CLAMP_SIZE 8
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#define SHP_DETAIL_ALPHA_SIZE 8
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#define ORB_DATA_NUM 10000
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#define ORB_BRIEF_NUM 15
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#define ORB_DUMMY_NUM 13
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#define FEC_MESH_BUF_MAX 7
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#define FEC_MESH_BUF_NUM 2
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#define MAX_BUF_IDXFD_NUM 64
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/************VIDIOC_PRIVATE*************/
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#define RKISPP_CMD_SET_INIT_MODULE \
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_IOW('V', BASE_VIDIOC_PRIVATE + 0, int)
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#define RKISPP_CMD_GET_FECBUF_INFO \
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_IOR('V', BASE_VIDIOC_PRIVATE + 1, struct rkispp_fecbuf_info)
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#define RKISPP_CMD_SET_FECBUF_SIZE \
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_IOW('V', BASE_VIDIOC_PRIVATE + 2, struct rkispp_fecbuf_size)
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#define RKISPP_CMD_TRIGGER_MODE \
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_IOW('V', BASE_VIDIOC_PRIVATE + 3, struct rkispp_trigger_mode)
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#define RKISPP_CMD_GET_TNRBUF_FD \
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_IOR('V', BASE_VIDIOC_PRIVATE + 4, struct rkispp_buf_idxfd)
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#define RKISPP_CMD_GET_NRBUF_FD \
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_IOR('V', BASE_VIDIOC_PRIVATE + 5, struct rkispp_buf_idxfd)
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/**independent fec video**/
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#define RKISPP_CMD_FEC_IN_OUT \
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_IOW('V', BASE_VIDIOC_PRIVATE + 10, struct rkispp_fec_in_out)
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/************EVENT_PRIVATE**************/
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#define RKISPP_V4L2_EVENT_TNR_COMPLETE \
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(V4L2_EVENT_PRIVATE_START + 3)
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struct rkispp_fec_in_out {
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int width;
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int height;
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int in_fourcc;
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int out_fourcc;
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int in_pic_fd;
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int out_pic_fd;
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int mesh_xint_fd;
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int mesh_xfra_fd;
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int mesh_yint_fd;
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int mesh_yfra_fd;
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};
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struct rkispp_buf_idxfd {
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u32 buf_num;
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u32 index[MAX_BUF_IDXFD_NUM];
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s32 dmafd[MAX_BUF_IDXFD_NUM];
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} __attribute__ ((packed));
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struct rkispp_trigger_mode {
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u32 module;
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u32 on;
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} __attribute__ ((packed));
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struct rkispp_tnr_config {
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u8 opty_en;
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u8 optc_en;
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u8 gain_en;
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u8 pk0_y;
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u8 pk1_y;
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u8 pk0_c;
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u8 pk1_c;
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u8 glb_gain_cur_sqrt;
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u8 sigma_x[TNR_SIGMA_CURVE_SIZE - 1];
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u8 gfcoef_y0[TNR_GFCOEF6_SIZE];
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u8 gfcoef_y1[TNR_GFCOEF3_SIZE];
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u8 gfcoef_y2[TNR_GFCOEF3_SIZE];
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u8 gfcoef_y3[TNR_GFCOEF3_SIZE];
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u8 gfcoef_yg0[TNR_GFCOEF6_SIZE];
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u8 gfcoef_yg1[TNR_GFCOEF3_SIZE];
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u8 gfcoef_yg2[TNR_GFCOEF3_SIZE];
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u8 gfcoef_yg3[TNR_GFCOEF3_SIZE];
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u8 gfcoef_yl0[TNR_GFCOEF6_SIZE];
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u8 gfcoef_yl1[TNR_GFCOEF3_SIZE];
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u8 gfcoef_yl2[TNR_GFCOEF3_SIZE];
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u8 gfcoef_cg0[TNR_GFCOEF6_SIZE];
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u8 gfcoef_cg1[TNR_GFCOEF3_SIZE];
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u8 gfcoef_cg2[TNR_GFCOEF3_SIZE];
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u8 gfcoef_cl0[TNR_GFCOEF6_SIZE];
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u8 gfcoef_cl1[TNR_GFCOEF3_SIZE];
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u8 weight_y[TNR_WEIGHT_Y_SIZE];
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u16 glb_gain_cur __attribute__((aligned(2)));
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u16 glb_gain_nxt;
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u16 glb_gain_cur_div;
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u16 txt_th1_y;
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u16 txt_th0_c;
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u16 txt_th1_c;
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u16 txt_thy_dlt;
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u16 txt_thc_dlt;
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u16 txt_th0_y;
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u16 sigma_y[TNR_SIGMA_CURVE_SIZE];
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u16 luma_curve[TNR_LUMA_CURVE_SIZE];
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u16 scale_yg[TNR_SCALE_YG_SIZE];
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u16 scale_yl[TNR_SCALE_YL_SIZE];
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u16 scale_cg[TNR_SCALE_CG_SIZE];
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u16 scale_y2cg[TNR_SCALE_Y2CG_SIZE];
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u16 scale_cl[TNR_SCALE_CL_SIZE];
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u16 scale_y2cl[TNR_SCALE_Y2CL_SIZE];
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} __attribute__ ((packed));
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struct rkispp_nr_config {
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u8 uvnr_step1_en;
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u8 uvnr_step2_en;
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u8 nr_gain_en;
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u8 uvnr_sd32_self_en;
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u8 uvnr_nobig_en;
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u8 uvnr_big_en;
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u8 uvnr_gain_1sigma;
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u8 uvnr_gain_offset;
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u8 uvnr_gain_t2gen;
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u8 uvnr_gain_iso;
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u8 uvnr_t1gen_m3alpha;
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u8 uvnr_t1flt_mode;
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u8 uvnr_t1flt_wtp;
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u8 uvnr_t2gen_m3alpha;
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u8 uvnr_t2gen_wtp;
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u8 uvnr_gain_uvgain[NR_UVNR_UVGAIN_SIZE];
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u8 uvnr_t1flt_wtq[NR_UVNR_T1FLT_WTQ_SIZE];
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u8 uvnr_t2gen_wtq[NR_UVNR_T2GEN_WTQ_SIZE];
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u8 uvnr_t2flt_wtp;
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u8 uvnr_t2flt_wt[NR_UVNR_T2FLT_WT_SIZE];
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u8 ynr_sgm_dx[NR_YNR_SGM_DX_SIZE];
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u8 ynr_lci[NR_YNR_CI_SIZE];
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u8 ynr_lgain_min[NR_YNR_LGAIN_MIN_SIZE];
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u8 ynr_lgain_max;
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u8 ynr_lmerge_bound;
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u8 ynr_lmerge_ratio;
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u8 ynr_lweit_flt[NR_YNR_LWEIT_FLT_SIZE];
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u8 ynr_hlci[NR_YNR_CI_SIZE];
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u8 ynr_lhci[NR_YNR_CI_SIZE];
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u8 ynr_hhci[NR_YNR_CI_SIZE];
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u8 ynr_hgain_sgm[NR_YNR_HGAIN_SGM_SIZE];
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u8 ynr_hweit_d[NR_YNR_HWEIT_D_SIZE];
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u8 ynr_hgrad_y[NR_YNR_HGRAD_Y_SIZE];
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u8 ynr_hmax_adjust;
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u8 ynr_hstrength;
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u8 ynr_lweit_cmp[NR_YNR_LWEIT_CMP_SIZE];
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u8 ynr_lmaxgain_lv4;
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u16 uvnr_t1flt_msigma __attribute__((aligned(2)));
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u16 uvnr_t2gen_msigma;
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u16 uvnr_t2flt_msigma;
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u16 ynr_lsgm_y[NR_YNR_SGM_Y_SIZE];
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u16 ynr_hsgm_y[NR_YNR_SGM_Y_SIZE];
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u16 ynr_hweit[NR_YNR_HWEIT_SIZE];
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u16 ynr_hstv_y[NR_YNR_HSTV_Y_SIZE];
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u16 ynr_st_scale[NR_YNR_ST_SCALE_SIZE];
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} __attribute__ ((packed));
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struct rkispp_sharp_config {
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u8 rotation;
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u8 scl_down_v;
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u8 scl_down_h;
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u8 tile_ycnt;
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u8 tile_xcnt;
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u8 alpha_adp_en;
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u8 yin_flt_en;
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u8 edge_avg_en;
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u8 ehf_th;
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u8 pbf_ratio;
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u8 edge_thed;
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u8 dir_min;
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u8 pbf_shf_bits;
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u8 mbf_shf_bits;
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u8 hbf_shf_bits;
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u8 m_ratio;
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u8 h_ratio;
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u8 pbf_k[SHP_PBF_KERNEL_SIZE];
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u8 mrf_k[SHP_MRF_KERNEL_SIZE];
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u8 mbf_k[SHP_MBF_KERNEL_SIZE];
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u8 hrf_k[SHP_HRF_KERNEL_SIZE];
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u8 hbf_k[SHP_HBF_KERNEL_SIZE];
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s8 eg_coef[SHP_EDGE_COEF_SIZE];
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u8 eg_smoth[SHP_EDGE_SMOTH_SIZE];
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u8 eg_gaus[SHP_EDGE_GAUS_SIZE];
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s8 dog_k[SHP_DOG_KERNEL_SIZE];
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u8 lum_point[SHP_LUM_POINT_SIZE];
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u8 pbf_sigma[SHP_SIGMA_SIZE];
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u8 lum_clp_m[SHP_LUM_CLP_SIZE];
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s8 lum_min_m[SHP_LUM_MIN_SIZE];
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u8 mbf_sigma[SHP_SIGMA_SIZE];
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u8 lum_clp_h[SHP_LUM_CLP_SIZE];
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u8 hbf_sigma[SHP_SIGMA_SIZE];
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u8 edge_lum_thed[SHP_EDGE_LUM_THED_SIZE];
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u8 clamp_pos[SHP_CLAMP_SIZE];
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u8 clamp_neg[SHP_CLAMP_SIZE];
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u8 detail_alpha[SHP_DETAIL_ALPHA_SIZE];
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u16 hbf_ratio __attribute__((aligned(2)));
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u16 smoth_th4;
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u16 l_alpha;
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u16 g_alpha;
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u16 rfl_ratio;
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u16 rfh_ratio;
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} __attribute__ ((packed));
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enum rkispp_fecbuf_stat {
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FEC_BUF_INIT = 0,
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FEC_BUF_WAIT2CHIP,
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FEC_BUF_CHIPINUSE,
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};
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struct rkispp_fecbuf_info {
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s32 buf_fd[FEC_MESH_BUF_MAX];
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u32 buf_size[FEC_MESH_BUF_MAX];
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} __attribute__ ((packed));
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struct rkispp_fecbuf_size {
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u32 meas_width;
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u32 meas_height;
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u32 meas_mode;
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int buf_cnt;
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} __attribute__ ((packed));
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struct rkispp_fec_head {
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enum rkispp_fecbuf_stat stat;
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u32 meshxf_oft;
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u32 meshyf_oft;
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u32 meshxi_oft;
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u32 meshyi_oft;
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} __attribute__ ((packed));
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struct rkispp_fec_config {
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u8 mesh_density;
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u8 crop_en;
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u16 crop_width __attribute__((aligned(2)));
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u16 crop_height;
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u32 mesh_size __attribute__((aligned(4)));
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s32 buf_fd;
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} __attribute__ ((packed));
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struct rkispp_orb_config {
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u8 limit_value;
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u32 max_feature __attribute__((aligned(4)));
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} __attribute__ ((packed));
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struct rkispp_buf_info {
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//s32 fd;
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u32 index;
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u32 size;
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} __attribute__ ((packed));
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/**
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* struct rkispp_params_cfghead - Rockchip ISPP Input Parameters Meta Data
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*
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* @module_en_update: mask the enable bits of which module should be updated
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* @module_ens: mask the enable value of each module, only update the module
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* which correspond bit was set in module_en_update
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* @module_cfg_update: mask the config bits of which module should be updated
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*/
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struct rkispp_params_cfghead {
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u32 module_en_update;
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u32 module_ens;
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u32 module_cfg_update;
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u32 frame_id;
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} __attribute__ ((packed));
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/**
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* struct rkispp_params_tnrcfg - Rockchip ISPP Input Parameters Meta Data
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*/
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struct rkispp_params_tnrcfg {
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struct rkispp_params_cfghead head;
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struct rkispp_tnr_config tnr_cfg;
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//struct rkispp_buf_info gain;
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//struct rkispp_buf_info image;
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} __attribute__ ((packed));
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/**
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* struct rkispp_params_nrcfg - Rockchip ISPP Input Parameters Meta Data
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*/
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struct rkispp_params_nrcfg {
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struct rkispp_params_cfghead head;
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struct rkispp_nr_config nr_cfg;
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struct rkispp_sharp_config shp_cfg;
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struct rkispp_orb_config orb_cfg;
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struct rkispp_buf_info gain;
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//struct rkispp_buf_info image;
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} __attribute__ ((packed));
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/**
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* struct rkispp_params_feccfg - Rockchip ISPP Input Parameters Meta Data
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*/
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struct rkispp_params_feccfg {
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struct rkispp_params_cfghead head;
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struct rkispp_fec_config fec_cfg;
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struct rkispp_buf_info image;
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} __attribute__ ((packed));
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struct rkispp_orb_data {
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u8 brief[ORB_BRIEF_NUM];
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u32 y : 13;
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u32 x : 13;
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u32 dmy1 : 6;
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u8 dmy2[ORB_DUMMY_NUM];
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} __attribute__ ((packed));
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/**
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* struct rkispp_stats_nrbuf - Rockchip ISPP Statistics
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*
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* @meas_type: measurement types
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* @frame_id: frame ID for sync
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* @data: statistics data
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*/
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struct rkispp_stats_nrbuf {
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struct rkispp_orb_data data[ORB_DATA_NUM];
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u32 total_num __attribute__((aligned(4)));
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u32 meas_type;
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u32 frame_id;
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struct rkispp_buf_info image;
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} __attribute__ ((packed));
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/**
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* struct rkispp_stats_tnrbuf - Rockchip ISPP Statistics
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*
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* @meas_type: measurement types
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* @frame_id: frame ID for sync
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*/
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struct rkispp_stats_tnrbuf {
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u32 meas_type;
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u32 frame_id;
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struct rkispp_buf_info gain;
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struct rkispp_buf_info gainkg;
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//struct rkispp_buf_info image;
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} __attribute__ ((packed));
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#endif
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