/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __T4020QDS_QIXIS_H__
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#define __T4020QDS_QIXIS_H__
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/* Definitions of QIXIS Registers for T4020QDS */
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/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
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#define BRDCFG4_EMISEL_MASK 0xE0
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#define BRDCFG4_EMISEL_SHIFT 5
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/* SYSCLK */
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#define QIXIS_SYSCLK_66 0x0
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#define QIXIS_SYSCLK_83 0x1
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#define QIXIS_SYSCLK_100 0x2
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#define QIXIS_SYSCLK_125 0x3
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#define QIXIS_SYSCLK_133 0x4
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#define QIXIS_SYSCLK_150 0x5
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#define QIXIS_SYSCLK_160 0x6
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#define QIXIS_SYSCLK_166 0x7
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/* DDRCLK */
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#define QIXIS_DDRCLK_66 0x0
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#define QIXIS_DDRCLK_100 0x1
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#define QIXIS_DDRCLK_125 0x2
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#define QIXIS_DDRCLK_133 0x3
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#define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */
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#define BRDCFG12_SD3EN_MASK 0x20
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#define BRDCFG12_SD3MX_MASK 0x08
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#define BRDCFG12_SD3MX_SLOT5 0x08
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#define BRDCFG12_SD3MX_SLOT6 0x00
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#define BRDCFG12_SD4EN_MASK 0x04
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#define BRDCFG12_SD4MX_MASK 0x03
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#define BRDCFG12_SD4MX_SLOT7 0x02
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#define BRDCFG12_SD4MX_SLOT8 0x01
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#define BRDCFG12_SD4MX_AURO_SATA 0x00
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#endif
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