/*
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* (C) Copyright 2009 SAMSUNG Electronics
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* Minkyu Kang <mk7.kang@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_MMC_H_
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#define __ASM_ARCH_MMC_H_
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#define S5P_MMC_DEV_OFFSET 0x10000
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#define SDHCI_CONTROL2 0x80
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#define SDHCI_CONTROL3 0x84
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#define SDHCI_CONTROL4 0x8C
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#define SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31)
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#define SDHCI_CTRL2_ENCMDCNFMSK (1 << 30)
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#define SDHCI_CTRL2_CDINVRXD3 (1 << 29)
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#define SDHCI_CTRL2_SLCARDOUT (1 << 28)
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#define SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
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#define SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
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#define SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
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#define SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
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#define SDHCI_CTRL2_LVLDAT_SHIFT (16)
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#define SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
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#define SDHCI_CTRL2_ENFBCLKTX (1 << 15)
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#define SDHCI_CTRL2_ENFBCLKRX (1 << 14)
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#define SDHCI_CTRL2_SDCDSEL (1 << 13)
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#define SDHCI_CTRL2_SDSIGPC (1 << 12)
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#define SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11)
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#define SDHCI_CTRL2_DFCNT_MASK(_x) ((_x) << 9)
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#define SDHCI_CTRL2_DFCNT_SHIFT (9)
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#define SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8)
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#define SDHCI_CTRL2_RWAITMODE (1 << 7)
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#define SDHCI_CTRL2_DISBUFRD (1 << 6)
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#define SDHCI_CTRL2_SELBASECLK_MASK(_x) ((_x) << 4)
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#define SDHCI_CTRL2_SELBASECLK_SHIFT (4)
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#define SDHCI_CTRL2_PWRSYNC (1 << 3)
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#define SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1)
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#define SDHCI_CTRL2_HWINITFIN (1 << 0)
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#define SDHCI_CTRL3_FCSEL3 (1 << 31)
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#define SDHCI_CTRL3_FCSEL2 (1 << 23)
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#define SDHCI_CTRL3_FCSEL1 (1 << 15)
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#define SDHCI_CTRL3_FCSEL0 (1 << 7)
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#define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16)
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#define SDHCI_CTRL4_DRIVE_SHIFT (16)
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#define SDHCI_MAX_HOSTS 4
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int s5p_sdhci_init(u32 regbase, int index, int bus_width);
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static inline int s5p_mmc_init(int index, int bus_width)
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{
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unsigned int base = samsung_get_base_mmc() +
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(S5P_MMC_DEV_OFFSET * index);
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return s5p_sdhci_init(base, index, bus_width);
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}
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int exynos_mmc_init(const void *blob);
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#endif
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