/*
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* Copyright (C) 2011 DENX Software Engineering GmbH
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* Heiko Schocher <hs@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _TIMER_DEFS_H_
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#define _TIMER_DEFS_H_
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struct davinci_timer {
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u_int32_t pid12;
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u_int32_t emumgt;
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u_int32_t na1;
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u_int32_t na2;
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u_int32_t tim12;
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u_int32_t tim34;
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u_int32_t prd12;
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u_int32_t prd34;
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u_int32_t tcr;
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u_int32_t tgcr;
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u_int32_t wdtcr;
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};
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#define DV_TIMER_TCR_ENAMODE_MASK 3
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#define DV_TIMER_TCR_ENAMODE12_SHIFT 6
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#define DV_TIMER_TCR_CLKSRC12_SHIFT 8
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#define DV_TIMER_TCR_READRSTMODE12_SHIFT 10
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#define DV_TIMER_TCR_CAPMODE12_SHIFT 11
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#define DV_TIMER_TCR_CAPVTMODE12_SHIFT 12
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#define DV_TIMER_TCR_ENAMODE34_SHIFT 22
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#define DV_TIMER_TCR_CLKSRC34_SHIFT 24
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#define DV_TIMER_TCR_READRSTMODE34_SHIFT 26
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#define DV_TIMER_TCR_CAPMODE34_SHIFT 27
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#define DV_TIMER_TCR_CAPEVTMODE12_SHIFT 28
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#define DV_WDT_ENABLE_SYS_RESET 0x00020000
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#define DV_WDT_TRIGGER_SYS_RESET 0x00020002
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#ifdef CONFIG_HW_WATCHDOG
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void davinci_hw_watchdog_enable(void);
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void davinci_hw_watchdog_reset(void);
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#endif
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#endif /* _TIMER_DEFS_H_ */
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