/*
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* (C) Copyright 2014-2016, Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/armv8/mmu.h>
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#include <asm/io.h>
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#include <asm/arch/mc_me_regs.h>
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#include "cpu.h"
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DECLARE_GLOBAL_DATA_PTR;
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u32 cpu_mask(void)
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{
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return readl(MC_ME_CS);
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}
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#ifndef CONFIG_SYS_DCACHE_OFF
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#define S32V234_IRAM_BASE 0x3e800000UL
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#define S32V234_IRAM_SIZE 0x800000UL
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#define S32V234_DRAM_BASE1 0x80000000UL
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#define S32V234_DRAM_SIZE1 0x40000000UL
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#define S32V234_DRAM_BASE2 0xC0000000UL
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#define S32V234_DRAM_SIZE2 0x20000000UL
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#define S32V234_PERIPH_BASE 0x40000000UL
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#define S32V234_PERIPH_SIZE 0x40000000UL
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static struct mm_region s32v234_mem_map[] = {
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{
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.virt = S32V234_IRAM_BASE,
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.phys = S32V234_IRAM_BASE,
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.size = S32V234_IRAM_SIZE,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE
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}, {
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.virt = S32V234_DRAM_BASE1,
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.phys = S32V234_DRAM_BASE1,
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.size = S32V234_DRAM_SIZE1,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE
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}, {
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.virt = S32V234_PERIPH_BASE,
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.phys = S32V234_PERIPH_BASE,
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.size = S32V234_PERIPH_SIZE,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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/* TODO: Do we need these? */
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/* | PTE_BLOCK_PXN | PTE_BLOCK_UXN */
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}, {
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.virt = S32V234_DRAM_BASE2,
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.phys = S32V234_DRAM_BASE2,
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.size = S32V234_DRAM_SIZE2,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
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PTE_BLOCK_OUTER_SHARE
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = s32v234_mem_map;
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#endif
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/*
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* Return the number of cores on this SOC.
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*/
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int cpu_numcores(void)
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{
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int numcores;
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u32 mask;
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mask = cpu_mask();
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numcores = hweight32(cpu_mask());
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/* Verify if M4 is deactivated */
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if (mask & 0x1)
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numcores--;
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return numcores;
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}
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#if defined(CONFIG_ARCH_EARLY_INIT_R)
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int arch_early_init_r(void)
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{
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int rv;
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asm volatile ("dsb sy");
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rv = fsl_s32v234_wake_seconday_cores();
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if (rv)
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printf("Did not wake secondary cores\n");
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asm volatile ("sev");
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return 0;
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}
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#endif /* CONFIG_ARCH_EARLY_INIT_R */
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