/*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#include <linux/sizes.h>
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#include <asm/system.h>
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#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
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#define ARM(x...)
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#define THUMB(x...) x
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#else
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#define ARM(x...) x
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#define THUMB(x...)
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#endif
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/*
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* v7_flush_dcache_all()
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*
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* Flush the whole D-cache.
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*
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* Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
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*
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* Note: copied from arch/arm/mm/cache-v7.S of Linux 4.4
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*/
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ENTRY(__v7_flush_dcache_all)
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dmb @ ensure ordering with previous memory accesses
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mrc p15, 1, r0, c0, c0, 1 @ read clidr
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mov r3, r0, lsr #23 @ move LoC into position
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ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
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beq finished @ if loc is 0, then no need to clean
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start_flush_levels:
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mov r10, #0 @ start clean at cache level 0
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flush_levels:
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add r2, r10, r10, lsr #1 @ work out 3x current cache level
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mov r1, r0, lsr r2 @ extract cache type bits from clidr
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and r1, r1, #7 @ mask of the bits for current cache only
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cmp r1, #2 @ see what cache we have at this level
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blt skip @ skip if no cache, or just i-cache
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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isb @ isb to sych the new cssr&csidr
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mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
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and r2, r1, #7 @ extract the length of the cache lines
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add r2, r2, #4 @ add 4 (line length offset)
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movw r4, #0x3ff
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ands r4, r4, r1, lsr #3 @ find maximum number on the way size
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clz r5, r4 @ find bit position of way size increment
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movw r7, #0x7fff
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ands r7, r7, r1, lsr #13 @ extract max number of the index size
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loop1:
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mov r9, r7 @ create working copy of max index
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loop2:
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ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
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THUMB( lsl r6, r4, r5 )
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THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
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ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
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THUMB( lsl r6, r9, r2 )
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THUMB( orr r11, r11, r6 ) @ factor index number into r11
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mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
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subs r9, r9, #1 @ decrement the index
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bge loop2
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subs r4, r4, #1 @ decrement the way
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bge loop1
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skip:
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add r10, r10, #2 @ increment cache number
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cmp r3, r10
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bgt flush_levels
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finished:
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mov r10, #0 @ swith back to cache level 0
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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dsb st
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isb
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bx lr
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ENDPROC(__v7_flush_dcache_all)
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ENTRY(v7_flush_dcache_all)
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ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} )
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THUMB( stmfd sp!, {r4-r7, r9-r11, lr} )
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bl __v7_flush_dcache_all
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ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
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THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} )
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bx lr
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ENDPROC(v7_flush_dcache_all)
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/*
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* v7_invalidate_dcache_all()
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*
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* Invalidate the whole D-cache.
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*
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* Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
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*
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* Note: copied from __v7_flush_dcache_all above with
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* mcr p15, 0, r11, c7, c14, 2
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* Replaced with:
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* mcr p15, 0, r11, c7, c6, 2
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*/
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ENTRY(__v7_invalidate_dcache_all)
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dmb @ ensure ordering with previous memory accesses
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mrc p15, 1, r0, c0, c0, 1 @ read clidr
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mov r3, r0, lsr #23 @ move LoC into position
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ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
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beq inval_finished @ if loc is 0, then no need to clean
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mov r10, #0 @ start clean at cache level 0
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inval_levels:
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add r2, r10, r10, lsr #1 @ work out 3x current cache level
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mov r1, r0, lsr r2 @ extract cache type bits from clidr
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and r1, r1, #7 @ mask of the bits for current cache only
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cmp r1, #2 @ see what cache we have at this level
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blt inval_skip @ skip if no cache, or just i-cache
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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isb @ isb to sych the new cssr&csidr
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mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
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and r2, r1, #7 @ extract the length of the cache lines
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add r2, r2, #4 @ add 4 (line length offset)
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movw r4, #0x3ff
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ands r4, r4, r1, lsr #3 @ find maximum number on the way size
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clz r5, r4 @ find bit position of way size increment
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movw r7, #0x7fff
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ands r7, r7, r1, lsr #13 @ extract max number of the index size
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inval_loop1:
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mov r9, r7 @ create working copy of max index
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inval_loop2:
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ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
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THUMB( lsl r6, r4, r5 )
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THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
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ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
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THUMB( lsl r6, r9, r2 )
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THUMB( orr r11, r11, r6 ) @ factor index number into r11
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mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way
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subs r9, r9, #1 @ decrement the index
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bge inval_loop2
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subs r4, r4, #1 @ decrement the way
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bge inval_loop1
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inval_skip:
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add r10, r10, #2 @ increment cache number
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cmp r3, r10
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bgt inval_levels
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inval_finished:
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mov r10, #0 @ swith back to cache level 0
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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dsb st
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isb
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bx lr
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ENDPROC(__v7_invalidate_dcache_all)
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ENTRY(v7_invalidate_dcache_all)
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ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} )
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THUMB( stmfd sp!, {r4-r7, r9-r11, lr} )
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bl __v7_invalidate_dcache_all
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ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
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THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} )
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bx lr
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ENDPROC(v7_invalidate_dcache_all)
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