/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#if defined (CONFIG_IMX)
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#include <asm/arch/imx-regs.h>
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int timer_init (void)
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{
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int i;
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/* setup GP Timer 1 */
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TCTL1 = TCTL_SWR;
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for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */
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TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */
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TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */
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/* Reset the timer */
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TCTL1 &= ~TCTL_TEN;
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TCTL1 |= TCTL_TEN; /* Enable timer */
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return (0);
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}
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/*
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* timer without interrupts
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*/
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ulong get_timer (ulong base)
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{
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return get_timer_masked() - base;
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}
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ulong get_timer_masked (void)
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{
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return TCN1;
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}
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void udelay_masked (unsigned long usec)
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{
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ulong endtime = get_timer_masked() + usec;
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signed long diff;
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do {
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ulong now = get_timer_masked ();
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diff = endtime - now;
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} while (diff >= 0);
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}
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void __udelay (unsigned long usec)
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{
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udelay_masked(usec);
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}
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/*
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* This function is derived from PowerPC code (read timebase as long long).
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* On ARM it just returns the timer value.
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*/
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On ARM it returns the number of timer ticks per second.
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*/
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ulong get_tbclk (void)
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{
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return CONFIG_SYS_HZ;
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}
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/*
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* Reset the cpu by setting up the watchdog timer and let him time out
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*/
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void reset_cpu (ulong ignored)
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{
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/* Disable watchdog and set Time-Out field to 0 */
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WCR = 0x00000000;
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/* Write Service Sequence */
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WSR = 0x00005555;
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WSR = 0x0000AAAA;
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/* Enable watchdog */
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WCR = 0x00000001;
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while (1);
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/*NOTREACHED*/
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}
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#endif /* defined (CONFIG_IMX) */
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