// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) Rockchip Electronics Co., Ltd.
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*
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* Author: Huang Lee <Putin.li@rock-chips.com>
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*/
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#define pr_fmt(fmt) "rga_policy: " fmt
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#include "rga_job.h"
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#include "rga_common.h"
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#include "rga_hw_config.h"
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#include "rga_debugger.h"
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#define GET_GCD(n1, n2) \
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({ \
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int i; \
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int gcd = 0; \
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for (i = 1; i <= (n1) && i <= (n2); i++) { \
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if ((n1) % i == 0 && (n2) % i == 0) \
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gcd = i; \
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} \
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gcd; \
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})
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#define GET_LCM(n1, n2, gcd) (((n1) * (n2)) / gcd)
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static int rga_set_feature(struct rga_req *rga_base)
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{
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int feature = 0;
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if (rga_base->render_mode == COLOR_FILL_MODE)
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feature |= RGA_COLOR_FILL;
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if (rga_base->render_mode == COLOR_PALETTE_MODE)
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feature |= RGA_COLOR_PALETTE;
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if (rga_base->color_key_max > 0 || rga_base->color_key_min > 0)
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feature |= RGA_COLOR_KEY;
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if ((rga_base->alpha_rop_flag >> 1) & 1)
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feature |= RGA_ROP_CALCULATE;
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if ((rga_base->alpha_rop_flag >> 8) & 1)
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feature |= RGA_NN_QUANTIZE;
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return feature;
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}
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static bool rga_check_resolution(const struct rga_rect_range *range, int width, int height)
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{
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if (width > range->max.width || height > range->max.height)
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return false;
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if (width < range->min.width || height < range->min.height)
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return false;
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return true;
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}
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static bool rga_check_format(const struct rga_hw_data *data,
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int rd_mode, int format, int win_num)
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{
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int i;
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bool matched = false;
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if (rd_mode == RGA_RASTER_MODE) {
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for (i = 0; i < data->win[win_num].num_of_raster_formats; i++) {
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if (format == data->win[win_num].raster_formats[i]) {
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matched = true;
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break;
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}
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}
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} else if (rd_mode == RGA_FBC_MODE) {
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for (i = 0; i < data->win[win_num].num_of_fbc_formats; i++) {
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if (format == data->win[win_num].fbc_formats[i]) {
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matched = true;
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break;
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}
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}
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} else if (rd_mode == RGA_TILE_MODE) {
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for (i = 0; i < data->win[win_num].num_of_tile_formats; i++) {
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if (format == data->win[win_num].tile_formats[i]) {
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matched = true;
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break;
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}
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}
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}
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return matched;
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}
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static bool rga_check_align(uint32_t byte_stride_align, uint32_t format, uint16_t w_stride)
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{
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int bit_stride, pixel_stride, align, gcd;
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pixel_stride = rga_get_pixel_stride_from_format(format);
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if (pixel_stride <= 0)
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return false;
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bit_stride = pixel_stride * w_stride;
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if (bit_stride % (byte_stride_align * 8) == 0)
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return true;
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if (DEBUGGER_EN(MSG)) {
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gcd = GET_GCD(pixel_stride, byte_stride_align * 8);
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align = GET_LCM(pixel_stride, byte_stride_align * 8, gcd) / pixel_stride;
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pr_info("unsupported width stride %d, 0x%x should be %d aligned!",
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w_stride, format, align);
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}
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return false;
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}
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static bool rga_check_src0(const struct rga_hw_data *data,
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struct rga_img_info_t *src0)
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{
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if (!rga_check_resolution(&data->input_range, src0->act_w, src0->act_h))
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return false;
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if (!rga_check_format(data, src0->rd_mode, src0->format, 0))
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return false;
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if (!rga_check_align(data->byte_stride_align, src0->format, src0->vir_w))
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return false;
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return true;
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}
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static bool rga_check_src1(const struct rga_hw_data *data,
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struct rga_img_info_t *src1)
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{
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if (!rga_check_resolution(&data->input_range, src1->act_w, src1->act_h))
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return false;
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if (!rga_check_format(data, src1->rd_mode, src1->format, 1))
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return false;
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if (!rga_check_align(data->byte_stride_align, src1->format, src1->vir_w))
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return false;
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return true;
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}
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static bool rga_check_dst(const struct rga_hw_data *data,
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struct rga_img_info_t *dst)
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{
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if (!rga_check_resolution(&data->output_range, dst->act_w, dst->act_h))
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return false;
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if (!rga_check_format(data, dst->rd_mode, dst->format, 2))
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return false;
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if (!rga_check_align(data->byte_stride_align, dst->format, dst->vir_w))
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return false;
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return true;
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}
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static bool rga_check_scale(const struct rga_hw_data *data,
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struct rga_req *rga_base)
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{
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struct rga_img_info_t *src0 = &rga_base->src;
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struct rga_img_info_t *dst = &rga_base->dst;
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int sw, sh;
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int dw, dh;
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sw = src0->act_w;
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sh = src0->act_h;
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if ((rga_base->sina == 65536 && rga_base->cosa == 0)
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|| (rga_base->sina == -65536 && rga_base->cosa == 0)) {
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dw = dst->act_h;
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dh = dst->act_w;
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} else {
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dw = dst->act_w;
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dh = dst->act_h;
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}
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if (sw > dw) {
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if ((sw >> data->max_downscale_factor) > dw)
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return false;
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} else if (sw < dw) {
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if ((sw << data->max_upscale_factor) < dw)
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return false;
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}
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if (sh > dh) {
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if ((sh >> data->max_downscale_factor) > dh)
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return false;
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} else if (sh < dh) {
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if ((sh << data->max_upscale_factor) < dh)
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return false;
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}
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return true;
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}
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int rga_job_assign(struct rga_job *job)
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{
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struct rga_img_info_t *src0 = &job->rga_command_base.src;
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struct rga_img_info_t *src1 = &job->rga_command_base.pat;
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struct rga_img_info_t *dst = &job->rga_command_base.dst;
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struct rga_req *rga_base = &job->rga_command_base;
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const struct rga_hw_data *data;
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struct rga_scheduler_t *scheduler = NULL;
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int feature;
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int core = RGA_NONE_CORE;
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int optional_cores = RGA_NONE_CORE;
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int specified_cores = RGA_NONE_CORE;
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int i;
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int min_of_job_count = -1;
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unsigned long flags;
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/* assigned by userspace */
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if (rga_base->core > RGA_NONE_CORE) {
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if (rga_base->core > RGA_CORE_MASK) {
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pr_err("invalid setting core by user\n");
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goto finish;
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} else if (rga_base->core & RGA_CORE_MASK)
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specified_cores = rga_base->core;
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}
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feature = rga_set_feature(rga_base);
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/* function */
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for (i = 0; i < rga_drvdata->num_of_scheduler; i++) {
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data = rga_drvdata->scheduler[i]->data;
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scheduler = rga_drvdata->scheduler[i];
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if ((specified_cores != RGA_NONE_CORE) &&
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(!(scheduler->core & specified_cores)))
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continue;
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if (DEBUGGER_EN(MSG))
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pr_info("start policy on core = %d", scheduler->core);
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if (scheduler->data->mmu == RGA_MMU &&
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job->flags & RGA_JOB_UNSUPPORT_RGA_MMU) {
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if (DEBUGGER_EN(MSG))
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pr_info("RGA2 only support under 4G memory!\n");
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continue;
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}
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if (feature > 0) {
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if (!(feature & data->feature)) {
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if (DEBUGGER_EN(MSG))
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pr_info("core = %d, break on feature",
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scheduler->core);
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continue;
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}
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}
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/* only colorfill need single win (colorpalette?) */
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if (!(feature & 1)) {
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if (src1->yrgb_addr > 0) {
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if ((!(src0->rd_mode & data->win[0].rd_mode)) ||
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(!(src1->rd_mode & data->win[1].rd_mode)) ||
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(!(dst->rd_mode & data->win[2].rd_mode))) {
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if (DEBUGGER_EN(MSG))
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pr_info("core = %d, ABC break on rd_mode",
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scheduler->core);
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continue;
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}
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} else {
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if ((!(src0->rd_mode & data->win[0].rd_mode)) ||
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(!(dst->rd_mode & data->win[2].rd_mode))) {
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if (DEBUGGER_EN(MSG))
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pr_info("core = %d, ABB break on rd_mode",
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scheduler->core);
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continue;
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}
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}
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if (!rga_check_scale(data, rga_base)) {
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if (DEBUGGER_EN(MSG))
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pr_info("core = %d, break on rga_check_scale",
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scheduler->core);
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continue;
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}
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if (!rga_check_src0(data, src0)) {
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if (DEBUGGER_EN(MSG))
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pr_info("core = %d, break on rga_check_src0",
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scheduler->core);
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continue;
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}
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if (src1->yrgb_addr > 0) {
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if (!rga_check_src1(data, src1)) {
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if (DEBUGGER_EN(MSG))
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pr_info("core = %d, break on rga_check_src1",
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scheduler->core);
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continue;
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}
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}
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}
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if (!rga_check_dst(data, dst)) {
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if (DEBUGGER_EN(MSG))
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pr_info("core = %d, break on rga_check_dst",
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scheduler->core);
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continue;
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}
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optional_cores |= scheduler->core;
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}
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if (DEBUGGER_EN(MSG))
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pr_info("optional_cores = %d\n", optional_cores);
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if (optional_cores == 0) {
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core = -1;
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pr_err("invalid function policy\n");
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goto finish;
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}
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for (i = 0; i < rga_drvdata->num_of_scheduler; i++) {
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scheduler = rga_drvdata->scheduler[i];
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if (optional_cores & scheduler->core) {
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spin_lock_irqsave(&scheduler->irq_lock, flags);
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if (scheduler->running_job == NULL) {
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core = scheduler->core;
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job->scheduler = scheduler;
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spin_unlock_irqrestore(&scheduler->irq_lock,
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flags);
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break;
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} else {
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if ((min_of_job_count == -1) ||
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(min_of_job_count > scheduler->job_count)) {
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min_of_job_count = scheduler->job_count;
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core = scheduler->core;
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job->scheduler = scheduler;
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}
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}
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spin_unlock_irqrestore(&scheduler->irq_lock, flags);
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}
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}
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/* TODO: need consider full load */
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finish:
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if (DEBUGGER_EN(MSG))
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pr_info("assign core: %d\n", core);
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return core;
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}
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