/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd
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*
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* author:
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* Herman Chen <herman.chen@rock-chips.com>
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*
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*/
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#ifndef __ROCKCHIP_MPP_RKVDEC2_H__
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#define __ROCKCHIP_MPP_RKVDEC2_H__
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#include <linux/dma-iommu.h>
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#include <linux/iopoll.h>
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#include <linux/of_platform.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/uaccess.h>
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#include <linux/regmap.h>
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#include <linux/kernel.h>
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#include <linux/thermal.h>
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#include <linux/notifier.h>
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#include <linux/proc_fs.h>
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#include <linux/nospec.h>
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#include <linux/rockchip/rockchip_sip.h>
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#include <linux/regulator/consumer.h>
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#include <soc/rockchip/pm_domains.h>
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#include <soc/rockchip/rockchip_sip.h>
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#include "mpp_debug.h"
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#include "mpp_common.h"
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#include "mpp_iommu.h"
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#define RKVDEC_DRIVER_NAME "mpp_rkvdec2"
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#define RKVDEC_SESSION_MAX_BUFFERS 40
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/* The maximum registers number of all the version */
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#define RKVDEC_REG_NUM 279
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#define RKVDEC_REG_HW_ID_INDEX 0
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#define RKVDEC_REG_START_INDEX 0
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#define RKVDEC_REG_END_INDEX 278
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#define REVDEC_GET_PROD_NUM(x) (((x) >> 16) & 0xffff)
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#define RKVDEC_REG_FORMAT_INDEX 9
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#define RKVDEC_GET_FORMAT(x) ((x) & 0x3ff)
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#define RKVDEC_REG_START_EN_BASE 0x28
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#define RKVDEC_REG_START_EN_INDEX 10
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#define RKVDEC_START_EN BIT(0)
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#define RKVDEC_REG_YSTRIDE_INDEX 20
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#define RKVDEC_REG_RLC_BASE 0x200
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#define RKVDEC_REG_RLC_BASE_INDEX (128)
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#define RKVDEC_REG_INT_EN 0x380
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#define RKVDEC_REG_INT_EN_INDEX (224)
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#define RKVDEC_SOFT_RESET_READY BIT(9)
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#define RKVDEC_CABAC_END_STA BIT(8)
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#define RKVDEC_COLMV_REF_ERR_STA BIT(7)
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#define RKVDEC_BUF_EMPTY_STA BIT(6)
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#define RKVDEC_TIMEOUT_STA BIT(5)
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#define RKVDEC_ERROR_STA BIT(4)
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#define RKVDEC_BUS_STA BIT(3)
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#define RKVDEC_READY_STA BIT(2)
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#define RKVDEC_IRQ_RAW BIT(1)
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#define RKVDEC_IRQ BIT(0)
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#define RKVDEC_INT_ERROR_MASK (RKVDEC_COLMV_REF_ERR_STA |\
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RKVDEC_BUF_EMPTY_STA |\
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RKVDEC_TIMEOUT_STA |\
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RKVDEC_ERROR_STA)
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/* perf sel reference register */
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#define RKVDEC_PERF_SEL_OFFSET 0x20000
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#define RKVDEC_PERF_SEL_NUM 64
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#define RKVDEC_PERF_SEL_BASE 0x424
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#define RKVDEC_SEL_VAL0_BASE 0x428
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#define RKVDEC_SEL_VAL1_BASE 0x42c
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#define RKVDEC_SEL_VAL2_BASE 0x430
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#define RKVDEC_SET_PERF_SEL(a, b, c) ((a) | ((b) << 8) | ((c) << 16))
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/* cache reference register */
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#define RKVDEC_REG_CACHE0_SIZE_BASE 0x51c
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#define RKVDEC_REG_CACHE1_SIZE_BASE 0x55c
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#define RKVDEC_REG_CACHE2_SIZE_BASE 0x59c
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#define RKVDEC_REG_CLR_CACHE0_BASE 0x510
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#define RKVDEC_REG_CLR_CACHE1_BASE 0x550
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#define RKVDEC_REG_CLR_CACHE2_BASE 0x590
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#define RKVDEC_CACHE_PERMIT_CACHEABLE_ACCESS BIT(0)
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#define RKVDEC_CACHE_PERMIT_READ_ALLOCATE BIT(1)
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#define RKVDEC_CACHE_LINE_SIZE_64_BYTES BIT(4)
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#define to_rkvdec2_task(task) \
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container_of(task, struct rkvdec2_task, mpp_task)
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#define to_rkvdec2_dev(dev) \
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container_of(dev, struct rkvdec2_dev, mpp)
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enum RKVDEC_FMT {
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RKVDEC_FMT_H265D = 0,
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RKVDEC_FMT_H264D = 1,
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RKVDEC_FMT_VP9D = 2,
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RKVDEC_FMT_AVS2 = 3,
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};
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#define RKVDEC_MAX_RCB_NUM (16)
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struct rcb_info_elem {
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u32 index;
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u32 size;
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};
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struct rkvdec2_rcb_info {
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u32 cnt;
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struct rcb_info_elem elem[RKVDEC_MAX_RCB_NUM];
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};
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struct rkvdec2_task {
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struct mpp_task mpp_task;
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enum MPP_CLOCK_MODE clk_mode;
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u32 reg[RKVDEC_REG_NUM];
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struct reg_offset_info off_inf;
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/* perf sel data back */
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u32 reg_sel[RKVDEC_PERF_SEL_NUM];
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u32 strm_addr;
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u32 irq_status;
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/* req for current task */
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u32 w_req_cnt;
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struct mpp_request w_reqs[MPP_MAX_MSG_NUM];
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u32 r_req_cnt;
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struct mpp_request r_reqs[MPP_MAX_MSG_NUM];
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/* image info */
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u32 width;
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u32 height;
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u32 pixels;
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/* task index for link table rnunning list */
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int slot_idx;
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u32 need_hack;
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/* event for task wait timeout or session timeout */
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wait_queue_head_t wait;
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};
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struct rkvdec2_session_priv {
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/* codec info from user */
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struct {
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/* show mode */
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u32 flag;
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/* item data */
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u64 val;
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} codec_info[DEC_INFO_BUTT];
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/* rcb_info for sram */
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struct rkvdec2_rcb_info rcb_inf;
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};
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struct rkvdec2_dev {
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struct mpp_dev mpp;
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/* sip smc reset lock */
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struct mutex sip_reset_lock;
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struct mpp_clk_info aclk_info;
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struct mpp_clk_info hclk_info;
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struct mpp_clk_info core_clk_info;
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struct mpp_clk_info cabac_clk_info;
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struct mpp_clk_info hevc_cabac_clk_info;
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u32 default_max_load;
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#ifdef CONFIG_ROCKCHIP_MPP_PROC_FS
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struct proc_dir_entry *procfs;
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#endif
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struct reset_control *rst_a;
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struct reset_control *rst_h;
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struct reset_control *rst_niu_a;
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struct reset_control *rst_niu_h;
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struct reset_control *rst_core;
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struct reset_control *rst_cabac;
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struct reset_control *rst_hevc_cabac;
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#ifdef CONFIG_PM_DEVFREQ
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struct regulator *vdd;
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struct devfreq *devfreq;
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unsigned long volt;
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unsigned long core_rate_hz;
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unsigned long core_last_rate_hz;
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struct ipa_power_model_data *model_data;
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struct thermal_cooling_device *devfreq_cooling;
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struct monitor_dev_info *mdev_info;
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#endif
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/* internal rcb-memory */
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u32 sram_size;
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u32 rcb_size;
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dma_addr_t rcb_iova;
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struct page *rcb_page;
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u32 rcb_min_width;
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/* for link mode */
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struct rkvdec_link_dev *link_dec;
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struct mpp_dma_buffer *fix;
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};
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void *rkvdec2_alloc_task(struct mpp_session *session,
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struct mpp_task_msgs *msgs);
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int rkvdec2_free_task(struct mpp_session *session, struct mpp_task *mpp_task);
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int rkvdec2_free_session(struct mpp_session *session);
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int rkvdec2_result(struct mpp_dev *mpp, struct mpp_task *mpp_task,
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struct mpp_task_msgs *msgs);
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#endif
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