// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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#include <linux/delay.h>
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#include <linux/console.h>
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#include <linux/serial_core.h>
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#include <linux/io.h>
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#define SE_UART_TX_TRANS_CFG (0x25C)
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#define SE_UART_TX_WORD_LEN (0x268)
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#define SE_UART_TX_STOP_BIT_LEN (0x26C)
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#define SE_UART_TX_TRANS_LEN (0x270)
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#define SE_UART_TX_PARITY_CFG (0x2A4)
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/* SE_UART_TRANS_CFG */
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#define UART_CTS_MASK (BIT(1))
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/* UART M_CMD OP codes */
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#define UART_START_TX (0x1)
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#define UART_OVERSAMPLING (32)
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#define DEF_FIFO_DEPTH_WORDS (16)
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#define DEF_TX_WM (2)
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#define DEF_FIFO_WIDTH_BITS (32)
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#define GENI_INIT_CFG_REVISION (0x0)
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#define GENI_S_INIT_CFG_REVISION (0x4)
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#define GENI_FORCE_DEFAULT_REG (0x20)
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#define GENI_OUTPUT_CTRL (0x24)
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#define GENI_CGC_CTRL (0x28)
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#define SE_GENI_STATUS (0x40)
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#define GENI_SER_M_CLK_CFG (0x48)
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#define GENI_CLK_CTRL_RO (0x60)
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#define GENI_IF_FIFO_DISABLE_RO (0x64)
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#define GENI_FW_REVISION_RO (0x68)
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#define SE_GENI_CLK_SEL (0x7C)
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#define SE_GENI_BYTE_GRAN (0x254)
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#define SE_GENI_TX_PACKING_CFG0 (0x260)
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#define SE_GENI_TX_PACKING_CFG1 (0x264)
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#define SE_GENI_M_CMD0 (0x600)
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#define SE_GENI_M_CMD_CTRL_REG (0x604)
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#define SE_GENI_M_IRQ_STATUS (0x610)
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#define SE_GENI_M_IRQ_EN (0x614)
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#define SE_GENI_M_IRQ_CLEAR (0x618)
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#define SE_GENI_TX_FIFOn (0x700)
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#define SE_GENI_TX_FIFO_STATUS (0x800)
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#define SE_GENI_TX_WATERMARK_REG (0x80C)
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#define SE_GENI_IOS (0x908)
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#define SE_GENI_M_GP_LENGTH (0x910)
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#define SE_IRQ_EN (0xE1C)
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#define SE_HW_PARAM_0 (0xE24)
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#define SE_HW_PARAM_1 (0xE28)
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/* GENI_OUTPUT_CTRL fields */
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#define DEFAULT_IO_OUTPUT_CTRL_MSK (GENMASK(6, 0))
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/* GENI_FORCE_DEFAULT_REG fields */
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#define FORCE_DEFAULT (BIT(0))
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/* GENI_CGC_CTRL fields */
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#define CFG_AHB_CLK_CGC_ON (BIT(0))
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#define CFG_AHB_WR_ACLK_CGC_ON (BIT(1))
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#define DATA_AHB_CLK_CGC_ON (BIT(2))
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#define SCLK_CGC_ON (BIT(3))
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#define TX_CLK_CGC_ON (BIT(4))
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#define RX_CLK_CGC_ON (BIT(5))
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#define EXT_CLK_CGC_ON (BIT(6))
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#define PROG_RAM_HCLK_OFF (BIT(8))
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#define PROG_RAM_SCLK_OFF (BIT(9))
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#define DEFAULT_CGC_EN (GENMASK(6, 0))
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/* GENI_STATUS fields */
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#define M_GENI_CMD_ACTIVE (BIT(0))
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/* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */
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#define SER_CLK_EN (BIT(0))
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#define CLK_DIV_MSK (GENMASK(15, 4))
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#define CLK_DIV_SHFT (4)
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/* CLK_CTRL_RO fields */
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/* FIFO_IF_DISABLE_RO fields */
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#define FIFO_IF_DISABLE (BIT(0))
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/* FW_REVISION_RO fields */
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#define FW_REV_PROTOCOL_MSK (GENMASK(15, 8))
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#define FW_REV_PROTOCOL_SHFT (8)
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#define FW_REV_VERSION_MSK (GENMASK(7, 0))
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/* GENI_CLK_SEL fields */
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#define CLK_SEL_MSK (GENMASK(2, 0))
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/* SE_GENI_DMA_MODE_EN */
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#define GENI_DMA_MODE_EN (BIT(0))
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/* GENI_M_CMD0 fields */
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#define M_OPCODE_MSK (GENMASK(31, 27))
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#define M_OPCODE_SHFT (27)
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#define M_PARAMS_MSK (GENMASK(26, 0))
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/* GENI_M_CMD_CTRL_REG */
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#define M_GENI_CMD_CANCEL BIT(2)
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#define M_GENI_CMD_ABORT BIT(1)
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#define M_GENI_DISABLE BIT(0)
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/* GENI_M_IRQ_EN fields */
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#define M_CMD_DONE_EN (BIT(0))
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#define M_CMD_OVERRUN_EN (BIT(1))
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#define M_ILLEGAL_CMD_EN (BIT(2))
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#define M_CMD_FAILURE_EN (BIT(3))
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#define M_CMD_CANCEL_EN (BIT(4))
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#define M_CMD_ABORT_EN (BIT(5))
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#define M_TIMESTAMP_EN (BIT(6))
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#define M_GP_SYNC_IRQ_0_EN (BIT(8))
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#define M_IO_DATA_DEASSERT_EN (BIT(22))
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#define M_IO_DATA_ASSERT_EN (BIT(23))
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#define M_TX_FIFO_RD_ERR_EN (BIT(28))
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#define M_TX_FIFO_WR_ERR_EN (BIT(29))
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#define M_TX_FIFO_WATERMARK_EN (BIT(30))
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#define M_SEC_IRQ_EN (BIT(31))
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#define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \
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M_IO_DATA_DEASSERT_EN | \
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M_IO_DATA_ASSERT_EN | M_TX_FIFO_RD_ERR_EN | \
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M_TX_FIFO_WR_ERR_EN)
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/* GENI_TX_FIFO_STATUS fields */
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#define TX_FIFO_WC (GENMASK(27, 0))
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/* SE_IRQ_EN fields */
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#define GENI_M_IRQ_EN (BIT(2))
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/* SE_HW_PARAM_0 fields */
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#define TX_FIFO_WIDTH_MSK (GENMASK(29, 24))
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#define TX_FIFO_WIDTH_SHFT (24)
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#define TX_FIFO_DEPTH_MSK (GENMASK(21, 16))
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#define TX_FIFO_DEPTH_SHFT (16)
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enum se_protocol_types {
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NONE,
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SPI,
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UART,
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I2C,
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I3C,
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};
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static void geni_write_reg_earlycon(unsigned int value,
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void __iomem *base, int offset)
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{
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writel_relaxed(value, (base + offset));
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}
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static unsigned int geni_read_reg_earlycon(void __iomem *base, int offset)
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{
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return readl_relaxed(base + offset);
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}
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static int get_se_proto_earlycon(void __iomem *base)
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{
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int proto;
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proto = ((geni_read_reg_earlycon(base, GENI_FW_REVISION_RO)
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& FW_REV_PROTOCOL_MSK) >> FW_REV_PROTOCOL_SHFT);
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return proto;
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}
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static void se_get_packing_config_earlycon(int bpw, int pack_words,
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bool msb_to_lsb, unsigned long *cfg0, unsigned long *cfg1)
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{
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u32 cfg[4] = {0};
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int len;
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int temp_bpw = bpw;
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int idx_start = (msb_to_lsb ? (bpw - 1) : 0);
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int idx = idx_start;
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int idx_delta = (msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE);
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int ceil_bpw = ((bpw & (BITS_PER_BYTE - 1)) ?
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((bpw & ~(BITS_PER_BYTE - 1)) + BITS_PER_BYTE) : bpw);
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int iter = (ceil_bpw * pack_words) >> 3;
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int i;
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if (unlikely(iter <= 0 || iter > 4)) {
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*cfg0 = 0;
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*cfg1 = 0;
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return;
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}
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for (i = 0; i < iter; i++) {
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len = (temp_bpw < BITS_PER_BYTE) ?
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(temp_bpw - 1) : BITS_PER_BYTE - 1;
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cfg[i] = ((idx << 5) | (msb_to_lsb << 4) | (len << 1));
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idx = ((temp_bpw - BITS_PER_BYTE) <= 0) ?
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((i + 1) * BITS_PER_BYTE) + idx_start :
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idx + idx_delta;
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temp_bpw = ((temp_bpw - BITS_PER_BYTE) <= 0) ?
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bpw : (temp_bpw - BITS_PER_BYTE);
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}
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cfg[iter - 1] |= 1;
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*cfg0 = cfg[0] | (cfg[1] << 10);
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*cfg1 = cfg[2] | (cfg[3] << 10);
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}
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static int se_geni_irq_en_earlycon(void __iomem *base)
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{
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unsigned int common_geni_m_irq_en;
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common_geni_m_irq_en = geni_read_reg_earlycon(base,
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SE_GENI_M_IRQ_EN);
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common_geni_m_irq_en |= M_COMMON_GENI_M_IRQ_EN;
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geni_write_reg_earlycon(common_geni_m_irq_en, base,
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SE_GENI_M_IRQ_EN);
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return 0;
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}
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static int se_io_set_mode_earlycon(void __iomem *base)
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{
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unsigned int io_mode;
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io_mode = geni_read_reg_earlycon(base, SE_IRQ_EN);
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io_mode |= (GENI_M_IRQ_EN);
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geni_write_reg_earlycon(io_mode, base, SE_IRQ_EN);
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return 0;
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}
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static void se_io_init_earlycon(void __iomem *base)
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{
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unsigned int io_op_ctrl;
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unsigned int geni_cgc_ctrl;
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geni_cgc_ctrl = geni_read_reg_earlycon(base, GENI_CGC_CTRL);
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geni_cgc_ctrl |= DEFAULT_CGC_EN;
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io_op_ctrl = DEFAULT_IO_OUTPUT_CTRL_MSK;
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geni_write_reg_earlycon(geni_cgc_ctrl, base, GENI_CGC_CTRL);
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geni_write_reg_earlycon(io_op_ctrl, base, GENI_OUTPUT_CTRL);
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geni_write_reg_earlycon(FORCE_DEFAULT, base,
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GENI_FORCE_DEFAULT_REG);
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}
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static int geni_se_init_earlycon(void __iomem *base, unsigned int rx_wm,
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unsigned int rx_rfr)
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{
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int ret;
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se_io_init_earlycon(base);
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ret = se_io_set_mode_earlycon(base);
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if (ret)
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return ret;
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ret = se_geni_irq_en_earlycon(base);
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return ret;
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}
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static int geni_se_select_fifo_mode_earlycon(void __iomem *base)
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{
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unsigned int common_geni_m_irq_en;
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geni_write_reg_earlycon(0xFFFFFFFF, base, SE_GENI_M_IRQ_CLEAR);
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geni_write_reg_earlycon(0xFFFFFFFF, base, SE_IRQ_EN);
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common_geni_m_irq_en = geni_read_reg_earlycon(base,
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SE_GENI_M_IRQ_EN);
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geni_write_reg_earlycon(common_geni_m_irq_en, base,
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SE_GENI_M_IRQ_EN);
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return 0;
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}
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struct msm_geni_serial_earlycon_port {
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struct uart_port uport;
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char name[20];
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unsigned int tx_fifo_depth;
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unsigned int tx_fifo_width;
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unsigned int tx_wm;
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unsigned int xmit_size;
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void *console_log;
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unsigned int cur_baud;
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};
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#define GET_DEV_PORT(uport) \
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container_of(uport, struct msm_geni_serial_earlycon_port, uport)
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static int get_clk_cfg(unsigned long clk_freq, unsigned long *ser_clk)
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{
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unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
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32000000, 48000000, 64000000, 80000000, 96000000, 100000000,
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102400000, 112000000, 120000000, 128000000};
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int i;
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int match = -1;
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for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
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if (clk_freq > root_freq[i])
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continue;
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if (!(root_freq[i] % clk_freq)) {
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match = i;
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break;
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}
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}
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if (match != -1)
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*ser_clk = root_freq[match];
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return match;
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}
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static int get_clk_div_rate(unsigned int baud, unsigned long *desired_clk_rate)
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{
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unsigned long ser_clk;
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int dfs_index;
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int clk_div = 0;
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*desired_clk_rate = baud * UART_OVERSAMPLING;
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dfs_index = get_clk_cfg(*desired_clk_rate, &ser_clk);
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if (dfs_index < 0) {
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clk_div = -EINVAL;
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goto exit_get_clk_div_rate;
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}
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clk_div = ser_clk / *desired_clk_rate;
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*desired_clk_rate = ser_clk;
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exit_get_clk_div_rate:
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return clk_div;
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}
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static void msm_geni_serial_wr_char(struct uart_port *uport, int ch)
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{
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geni_write_reg_earlycon(ch, uport->membase, SE_GENI_TX_FIFOn);
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/*
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* Ensure FIFO write clear goes through before
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* next iteration.
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*/
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mb();
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}
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static int msm_geni_serial_poll_bit(struct uart_port *uport,
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int offset, int bit_field, bool set)
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{
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int iter = 0;
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unsigned int reg;
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bool met = false;
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struct msm_geni_serial_earlycon_port *port = NULL;
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bool cond = false;
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unsigned int baud = 115200;
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unsigned int fifo_bits = DEF_FIFO_DEPTH_WORDS * DEF_FIFO_WIDTH_BITS;
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unsigned long total_iter = 1000;
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if (uport->private_data && !uart_console(uport)) {
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port = GET_DEV_PORT(uport);
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baud = (port->cur_baud ? port->cur_baud : 115200);
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fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
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/*
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* Total polling iterations based on FIFO worth of bytes to be
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* sent at current baud .Add a little fluff to the wait.
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*/
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total_iter = ((fifo_bits * USEC_PER_SEC) / baud) / 10;
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total_iter += 50;
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}
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while (iter < total_iter) {
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reg = geni_read_reg_earlycon(uport->membase, offset);
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cond = reg & bit_field;
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if (cond == set) {
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met = true;
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break;
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}
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udelay(10);
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iter++;
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}
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return met;
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}
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static void msm_geni_serial_poll_cancel_tx(struct uart_port *uport)
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{
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int done = 0;
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unsigned int irq_clear = M_CMD_DONE_EN;
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done = msm_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
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M_CMD_DONE_EN, true);
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if (!done) {
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geni_write_reg_earlycon(M_GENI_CMD_ABORT, uport->membase,
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SE_GENI_M_CMD_CTRL_REG);
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irq_clear |= M_CMD_ABORT_EN;
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msm_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
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M_CMD_ABORT_EN, true);
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}
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geni_write_reg_earlycon(irq_clear, uport->membase,
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SE_GENI_M_IRQ_CLEAR);
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}
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static void msm_geni_serial_setup_tx(struct uart_port *uport,
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unsigned int xmit_size)
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{
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u32 m_cmd = 0;
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geni_write_reg_earlycon(xmit_size, uport->membase,
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SE_UART_TX_TRANS_LEN);
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m_cmd |= (UART_START_TX << M_OPCODE_SHFT);
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geni_write_reg_earlycon(m_cmd, uport->membase, SE_GENI_M_CMD0);
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/*
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* Writes to enable the primary sequencer should go through before
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* exiting this function.
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*/
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mb();
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}
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static void
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__msm_geni_serial_console_write(struct uart_port *uport, const char *s,
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unsigned int count)
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{
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int new_line = 0;
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int i;
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int bytes_to_send = count;
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int fifo_depth = DEF_FIFO_DEPTH_WORDS;
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int tx_wm = DEF_TX_WM;
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for (i = 0; i < count; i++) {
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if (s[i] == '\n')
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new_line++;
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}
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bytes_to_send += new_line;
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geni_write_reg_earlycon(tx_wm, uport->membase,
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SE_GENI_TX_WATERMARK_REG);
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msm_geni_serial_setup_tx(uport, bytes_to_send);
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i = 0;
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while (i < count) {
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u32 chars_to_write = 0;
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u32 avail_fifo_bytes = (fifo_depth - tx_wm);
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/*
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* If the WM bit never set, then the Tx state machine is not
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* in a valid state, so break, cancel/abort any existing
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* command. Unfortunately the current data being written is
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* lost.
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*/
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while (!msm_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
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M_TX_FIFO_WATERMARK_EN, true))
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break;
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chars_to_write = min((unsigned int)(count - i),
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avail_fifo_bytes);
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if ((chars_to_write << 1) > avail_fifo_bytes)
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chars_to_write = (avail_fifo_bytes >> 1);
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uart_console_write(uport, (s + i), chars_to_write,
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msm_geni_serial_wr_char);
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geni_write_reg_earlycon(M_TX_FIFO_WATERMARK_EN,
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uport->membase, SE_GENI_M_IRQ_CLEAR);
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/* Ensure this goes through before polling for WM IRQ again.*/
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mb();
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i += chars_to_write;
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}
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msm_geni_serial_poll_cancel_tx(uport);
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}
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|
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static void
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msm_geni_serial_early_console_write(struct console *con, const char *s,
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unsigned int n)
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{
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struct earlycon_device *dev = con->data;
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__msm_geni_serial_console_write(&dev->port, s, n);
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}
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static int __init
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msm_geni_serial_earlycon_setup(struct earlycon_device *dev,
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const char *opt)
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{
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struct uart_port *uport = &dev->port;
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int ret = 0;
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u32 tx_trans_cfg = 0;
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u32 tx_parity_cfg = 0;
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u32 rx_trans_cfg = 0;
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u32 rx_parity_cfg = 0;
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u32 stop_bit = 0;
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u32 rx_stale = 0;
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u32 bits_per_char = 0;
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u32 s_clk_cfg = 0;
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u32 baud = 115200;
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int clk_div;
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unsigned long clk_rate;
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unsigned long cfg0, cfg1;
|
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if (!uport->membase) {
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ret = -ENOMEM;
|
goto exit_geni_serial_earlyconsetup;
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}
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if (get_se_proto_earlycon(uport->membase) != UART) {
|
ret = -ENXIO;
|
goto exit_geni_serial_earlyconsetup;
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}
|
|
/*
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* Ignore Flow control.
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* Disable Tx Parity.
|
* Don't check Parity during Rx.
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* Disable Rx Parity.
|
* n = 8.
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* Stop bit = 0.
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* Stale timeout in bit-time (3 chars worth).
|
*/
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tx_trans_cfg |= UART_CTS_MASK;
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tx_parity_cfg = 0;
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rx_trans_cfg = 0;
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rx_parity_cfg = 0;
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bits_per_char = 0x8;
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stop_bit = 0;
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rx_stale = 0x18;
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clk_div = get_clk_div_rate(baud, &clk_rate);
|
if (clk_div <= 0) {
|
ret = -EINVAL;
|
goto exit_geni_serial_earlyconsetup;
|
}
|
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if (IS_ENABLED(CONFIG_SERIAL_MSM_GENI_HALF_SAMPLING))
|
clk_div *= 2;
|
|
s_clk_cfg |= SER_CLK_EN;
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s_clk_cfg |= (clk_div << CLK_DIV_SHFT);
|
|
/*
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* Make an unconditional cancel on the main sequencer to reset
|
* it else we could end up in data loss scenarios.
|
*/
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geni_write_reg_earlycon(0x21, uport->membase, GENI_SER_M_CLK_CFG);
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geni_read_reg_earlycon(uport->membase, GENI_SER_M_CLK_CFG);
|
|
msm_geni_serial_poll_cancel_tx(uport);
|
|
se_get_packing_config_earlycon(8, 1, false, &cfg0, &cfg1);
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geni_se_init_earlycon(uport->membase, (DEF_FIFO_DEPTH_WORDS >> 1),
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(DEF_FIFO_DEPTH_WORDS - 2));
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geni_se_select_fifo_mode_earlycon(uport->membase);
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geni_write_reg_earlycon(cfg0, uport->membase,
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SE_GENI_TX_PACKING_CFG0);
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geni_write_reg_earlycon(cfg1, uport->membase,
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SE_GENI_TX_PACKING_CFG1);
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geni_write_reg_earlycon(tx_trans_cfg, uport->membase,
|
SE_UART_TX_TRANS_CFG);
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geni_write_reg_earlycon(tx_parity_cfg, uport->membase,
|
SE_UART_TX_PARITY_CFG);
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geni_write_reg_earlycon(bits_per_char, uport->membase,
|
SE_UART_TX_WORD_LEN);
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geni_write_reg_earlycon(stop_bit, uport->membase,
|
SE_UART_TX_STOP_BIT_LEN);
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geni_write_reg_earlycon(s_clk_cfg, uport->membase,
|
GENI_SER_M_CLK_CFG);
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geni_read_reg_earlycon(uport->membase,
|
GENI_SER_M_CLK_CFG);
|
|
dev->con->write = msm_geni_serial_early_console_write;
|
dev->con->setup = NULL;
|
/*
|
* Ensure that the early console setup completes before
|
* returning.
|
*/
|
mb();
|
exit_geni_serial_earlyconsetup:
|
return ret;
|
}
|
OF_EARLYCON_DECLARE(msm_geni_serial, "qcom,msm-geni-console",
|
msm_geni_serial_earlycon_setup);
|
