/*************************************************************************/ /*!
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@Title Test Chip Framework PDP register definitions
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@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
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@Description Autogenerated C -- do not edit
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Generated from tcf_pll.def
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@License Dual MIT/GPLv2
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The contents of this file are subject to the MIT license as set out below.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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Alternatively, the contents of this file may be used under the terms of
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the GNU General Public License Version 2 ("GPL") in which case the provisions
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of GPL are applicable instead of those above.
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If you wish to allow use of your version of this file only under the terms of
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GPL, and not to allow others to use your version of this file under the terms
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of the MIT license, indicate your decision by deleting the provisions above
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and replace them with the notice and other provisions required by GPL as set
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out in the file called "GPL-COPYING" included in this distribution. If you do
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not delete the provisions above, a recipient may use your version of this file
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under the terms of either the MIT license or GPL.
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This License is also included in this distribution in the file called
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"MIT-COPYING".
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EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
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PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
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COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/ /**************************************************************************/
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#if !defined(_TCF_PLL_H_)
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#define _TCF_PLL_H_
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/*
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Register PLL_DDR2_CLK0
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*/
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#define TCF_PLL_PLL_DDR2_CLK0 0x0000
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#define DDR2_PLL_CLK0_PHS_MASK 0x00300000U
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#define DDR2_PLL_CLK0_PHS_SHIFT 20
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#define DDR2_PLL_CLK0_PHS_SIGNED 0
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#define DDR2_PLL_CLK0_MS_MASK 0x00030000U
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#define DDR2_PLL_CLK0_MS_SHIFT 16
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#define DDR2_PLL_CLK0_MS_SIGNED 0
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#define DDR2_PLL_CLK0_FREQ_MASK 0x000001FFU
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#define DDR2_PLL_CLK0_FREQ_SHIFT 0
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#define DDR2_PLL_CLK0_FREQ_SIGNED 0
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/*
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Register PLL_DDR2_CLK1TO5
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*/
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#define TCF_PLL_PLL_DDR2_CLK1TO5 0x0008
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#define DDR2_PLL_CLK1TO5_PHS_MASK 0x3FF00000U
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#define DDR2_PLL_CLK1TO5_PHS_SHIFT 20
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#define DDR2_PLL_CLK1TO5_PHS_SIGNED 0
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#define DDR2_PLL_CLK1TO5_MS_MASK 0x000FFC00U
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#define DDR2_PLL_CLK1TO5_MS_SHIFT 10
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#define DDR2_PLL_CLK1TO5_MS_SIGNED 0
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#define DDR2_PLL_CLK1TO5_FREQ_MASK 0x000003FFU
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#define DDR2_PLL_CLK1TO5_FREQ_SHIFT 0
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#define DDR2_PLL_CLK1TO5_FREQ_SIGNED 0
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/*
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Register PLL_DDR2_DRP_GO
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*/
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#define TCF_PLL_PLL_DDR2_DRP_GO 0x0010
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#define PLL_DDR2_DRP_GO_MASK 0x00000001U
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#define PLL_DDR2_DRP_GO_SHIFT 0
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#define PLL_DDR2_DRP_GO_SIGNED 0
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/*
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Register PLL_PDP_CLK0
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*/
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#define TCF_PLL_PLL_PDP_CLK0 0x0018
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#define PDP_PLL_CLK0_PHS_MASK 0x00300000U
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#define PDP_PLL_CLK0_PHS_SHIFT 20
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#define PDP_PLL_CLK0_PHS_SIGNED 0
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#define PDP_PLL_CLK0_MS_MASK 0x00030000U
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#define PDP_PLL_CLK0_MS_SHIFT 16
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#define PDP_PLL_CLK0_MS_SIGNED 0
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#define PDP_PLL_CLK0_FREQ_MASK 0x000001FFU
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#define PDP_PLL_CLK0_FREQ_SHIFT 0
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#define PDP_PLL_CLK0_FREQ_SIGNED 0
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/*
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Register PLL_PDP_CLK1TO5
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*/
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#define TCF_PLL_PLL_PDP_CLK1TO5 0x0020
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#define PDP_PLL_CLK1TO5_PHS_MASK 0x3FF00000U
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#define PDP_PLL_CLK1TO5_PHS_SHIFT 20
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#define PDP_PLL_CLK1TO5_PHS_SIGNED 0
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#define PDP_PLL_CLK1TO5_MS_MASK 0x000FFC00U
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#define PDP_PLL_CLK1TO5_MS_SHIFT 10
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#define PDP_PLL_CLK1TO5_MS_SIGNED 0
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#define PDP_PLL_CLK1TO5_FREQ_MASK 0x000003FFU
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#define PDP_PLL_CLK1TO5_FREQ_SHIFT 0
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#define PDP_PLL_CLK1TO5_FREQ_SIGNED 0
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/*
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Register PLL_PDP_DRP_GO
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*/
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#define TCF_PLL_PLL_PDP_DRP_GO 0x0028
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#define PLL_PDP_DRP_GO_MASK 0x00000001U
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#define PLL_PDP_DRP_GO_SHIFT 0
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#define PLL_PDP_DRP_GO_SIGNED 0
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/*
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Register PLL_PDP2_CLK0
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*/
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#define TCF_PLL_PLL_PDP2_CLK0 0x0030
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#define PDP2_PLL_CLK0_PHS_MASK 0x00300000U
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#define PDP2_PLL_CLK0_PHS_SHIFT 20
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#define PDP2_PLL_CLK0_PHS_SIGNED 0
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#define PDP2_PLL_CLK0_MS_MASK 0x00030000U
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#define PDP2_PLL_CLK0_MS_SHIFT 16
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#define PDP2_PLL_CLK0_MS_SIGNED 0
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#define PDP2_PLL_CLK0_FREQ_MASK 0x000001FFU
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#define PDP2_PLL_CLK0_FREQ_SHIFT 0
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#define PDP2_PLL_CLK0_FREQ_SIGNED 0
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/*
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Register PLL_PDP2_CLK1TO5
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*/
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#define TCF_PLL_PLL_PDP2_CLK1TO5 0x0038
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#define PDP2_PLL_CLK1TO5_PHS_MASK 0x3FF00000U
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#define PDP2_PLL_CLK1TO5_PHS_SHIFT 20
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#define PDP2_PLL_CLK1TO5_PHS_SIGNED 0
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#define PDP2_PLL_CLK1TO5_MS_MASK 0x000FFC00U
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#define PDP2_PLL_CLK1TO5_MS_SHIFT 10
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#define PDP2_PLL_CLK1TO5_MS_SIGNED 0
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#define PDP2_PLL_CLK1TO5_FREQ_MASK 0x000003FFU
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#define PDP2_PLL_CLK1TO5_FREQ_SHIFT 0
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#define PDP2_PLL_CLK1TO5_FREQ_SIGNED 0
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/*
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Register PLL_PDP2_DRP_GO
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*/
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#define TCF_PLL_PLL_PDP2_DRP_GO 0x0040
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#define PLL_PDP2_DRP_GO_MASK 0x00000001U
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#define PLL_PDP2_DRP_GO_SHIFT 0
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#define PLL_PDP2_DRP_GO_SIGNED 0
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/*
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Register PLL_CORE_CLK0
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*/
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#define TCF_PLL_PLL_CORE_CLK0 0x0048
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#define CORE_PLL_CLK0_PHS_MASK 0x00300000U
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#define CORE_PLL_CLK0_PHS_SHIFT 20
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#define CORE_PLL_CLK0_PHS_SIGNED 0
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#define CORE_PLL_CLK0_MS_MASK 0x00030000U
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#define CORE_PLL_CLK0_MS_SHIFT 16
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#define CORE_PLL_CLK0_MS_SIGNED 0
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#define CORE_PLL_CLK0_FREQ_MASK 0x000001FFU
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#define CORE_PLL_CLK0_FREQ_SHIFT 0
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#define CORE_PLL_CLK0_FREQ_SIGNED 0
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/*
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Register PLL_CORE_CLK1TO5
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*/
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#define TCF_PLL_PLL_CORE_CLK1TO5 0x0050
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#define CORE_PLL_CLK1TO5_PHS_MASK 0x3FF00000U
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#define CORE_PLL_CLK1TO5_PHS_SHIFT 20
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#define CORE_PLL_CLK1TO5_PHS_SIGNED 0
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#define CORE_PLL_CLK1TO5_MS_MASK 0x000FFC00U
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#define CORE_PLL_CLK1TO5_MS_SHIFT 10
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#define CORE_PLL_CLK1TO5_MS_SIGNED 0
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#define CORE_PLL_CLK1TO5_FREQ_MASK 0x000003FFU
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#define CORE_PLL_CLK1TO5_FREQ_SHIFT 0
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#define CORE_PLL_CLK1TO5_FREQ_SIGNED 0
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/*
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Register PLL_CORE_DRP_GO
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*/
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#define TCF_PLL_PLL_CORE_DRP_GO 0x0058
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#define PLL_CORE_DRP_GO_MASK 0x00000001U
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#define PLL_CORE_DRP_GO_SHIFT 0
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#define PLL_CORE_DRP_GO_SIGNED 0
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/*
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Register PLL_SYSIF_CLK0
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*/
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#define TCF_PLL_PLL_SYSIF_CLK0 0x0060
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#define SYSIF_PLL_CLK0_PHS_MASK 0x00300000U
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#define SYSIF_PLL_CLK0_PHS_SHIFT 20
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#define SYSIF_PLL_CLK0_PHS_SIGNED 0
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#define SYSIF_PLL_CLK0_MS_MASK 0x00030000U
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#define SYSIF_PLL_CLK0_MS_SHIFT 16
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#define SYSIF_PLL_CLK0_MS_SIGNED 0
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#define SYSIF_PLL_CLK0_FREQ_MASK 0x000001FFU
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#define SYSIF_PLL_CLK0_FREQ_SHIFT 0
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#define SYSIF_PLL_CLK0_FREQ_SIGNED 0
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/*
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Register PLL_SYSIF_CLK1TO5
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*/
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#define TCF_PLL_PLL_SYSIF_CLK1TO5 0x0068
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#define SYSIF_PLL_CLK1TO5_PHS_MASK 0x3FF00000U
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#define SYSIF_PLL_CLK1TO5_PHS_SHIFT 20
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#define SYSIF_PLL_CLK1TO5_PHS_SIGNED 0
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#define SYSIF_PLL_CLK1TO5_MS_MASK 0x000FFC00U
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#define SYSIF_PLL_CLK1TO5_MS_SHIFT 10
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#define SYSIF_PLL_CLK1TO5_MS_SIGNED 0
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#define SYSIF_PLL_CLK1TO5_FREQ_MASK 0x000003FFU
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#define SYSIF_PLL_CLK1TO5_FREQ_SHIFT 0
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#define SYSIF_PLL_CLK1TO5_FREQ_SIGNED 0
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/*
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Register PLL_SYS_DRP_GO
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*/
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#define TCF_PLL_PLL_SYS_DRP_GO 0x0070
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#define PLL_SYS_DRP_GO_MASK 0x00000001U
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#define PLL_SYS_DRP_GO_SHIFT 0
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#define PLL_SYS_DRP_GO_SIGNED 0
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/*
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Register PLL_MEMIF_CLK0
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*/
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#define TCF_PLL_PLL_MEMIF_CLK0 0x0078
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#define MEMIF_PLL_CLK0_PHS_MASK 0x00300000U
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#define MEMIF_PLL_CLK0_PHS_SHIFT 20
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#define MEMIF_PLL_CLK0_PHS_SIGNED 0
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#define MEMIF_PLL_CLK0_MS_MASK 0x00030000U
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#define MEMIF_PLL_CLK0_MS_SHIFT 16
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#define MEMIF_PLL_CLK0_MS_SIGNED 0
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#define MEMIF_PLL_CLK0_FREQ_MASK 0x000001FFU
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#define MEMIF_PLL_CLK0_FREQ_SHIFT 0
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#define MEMIF_PLL_CLK0_FREQ_SIGNED 0
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/*
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Register PLL_MEMIF_CLK1TO5
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*/
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#define TCF_PLL_PLL_MEMIF_CLK1TO5 0x0080
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#define MEMIF_PLL_CLK1TO5_PHS_MASK 0x3FF00000U
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#define MEMIF_PLL_CLK1TO5_PHS_SHIFT 20
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#define MEMIF_PLL_CLK1TO5_PHS_SIGNED 0
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#define MEMIF_PLL_CLK1TO5_MS_MASK 0x000FFC00U
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#define MEMIF_PLL_CLK1TO5_MS_SHIFT 10
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#define MEMIF_PLL_CLK1TO5_MS_SIGNED 0
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#define MEMIF_PLL_CLK1TO5_FREQ_MASK 0x000003FFU
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#define MEMIF_PLL_CLK1TO5_FREQ_SHIFT 0
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#define MEMIF_PLL_CLK1TO5_FREQ_SIGNED 0
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/*
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Register PLL_MEM_DRP_GO
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*/
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#define TCF_PLL_PLL_MEM_DRP_GO 0x0088
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#define PLL_MEM_DRP_GO_MASK 0x00000001U
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#define PLL_MEM_DRP_GO_SHIFT 0
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#define PLL_MEM_DRP_GO_SIGNED 0
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/*
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Register PLL_ALL_DRP_GO
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*/
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#define TCF_PLL_PLL_ALL_DRP_GO 0x0090
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#define PLL_ALL_DRP_GO_MASK 0x00000001U
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#define PLL_ALL_DRP_GO_SHIFT 0
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#define PLL_ALL_DRP_GO_SIGNED 0
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/*
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Register PLL_DRP_STATUS
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*/
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#define TCF_PLL_PLL_DRP_STATUS 0x0098
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#define PLL_LOCKS_MASK 0x00003F00U
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#define PLL_LOCKS_SHIFT 8
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#define PLL_LOCKS_SIGNED 0
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#define PLL_DRP_GOOD_MASK 0x0000003FU
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#define PLL_DRP_GOOD_SHIFT 0
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#define PLL_DRP_GOOD_SIGNED 0
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#endif /* !defined(_TCF_PLL_H_) */
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/*****************************************************************************
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End of file (tcf_pll.h)
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*****************************************************************************/
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