// SPDX-License-Identifier: GPL-2.0+
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/*
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* Command support for NI general purpose counters
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*
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* Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
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*/
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/*
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* Module: ni_tiocmd
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* Description: National Instruments general purpose counters command support
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* Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
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* Herman.Bruyninckx@mech.kuleuven.ac.be,
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* Wim.Meeussen@mech.kuleuven.ac.be,
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* Klaas.Gadeyne@mech.kuleuven.ac.be,
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* Frank Mori Hess <fmhess@users.sourceforge.net>
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* Updated: Fri, 11 Apr 2008 12:32:35 +0100
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* Status: works
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*
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* This module is not used directly by end-users. Rather, it
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* is used by other drivers (for example ni_660x and ni_pcimio)
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* to provide command support for NI's general purpose counters.
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* It was originally split out of ni_tio.c to stop the 'ni_tio'
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* module depending on the 'mite' module.
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*
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* References:
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* DAQ 660x Register-Level Programmer Manual (NI 370505A-01)
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* DAQ 6601/6602 User Manual (NI 322137B-01)
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* 340934b.pdf DAQ-STC reference manual
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*
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* TODO: Support use of both banks X and Y
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*/
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#include <linux/module.h>
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#include "ni_tio_internal.h"
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#include "mite.h"
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static void ni_tio_configure_dma(struct ni_gpct *counter,
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bool enable, bool read)
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{
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struct ni_gpct_device *counter_dev = counter->counter_dev;
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unsigned int cidx = counter->counter_index;
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unsigned int mask;
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unsigned int bits;
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mask = GI_READ_ACKS_IRQ | GI_WRITE_ACKS_IRQ;
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bits = 0;
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if (enable) {
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if (read)
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bits |= GI_READ_ACKS_IRQ;
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else
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bits |= GI_WRITE_ACKS_IRQ;
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}
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ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), mask, bits);
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switch (counter_dev->variant) {
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case ni_gpct_variant_e_series:
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break;
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case ni_gpct_variant_m_series:
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case ni_gpct_variant_660x:
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mask = GI_DMA_ENABLE | GI_DMA_INT_ENA | GI_DMA_WRITE;
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bits = 0;
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if (enable)
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bits |= GI_DMA_ENABLE | GI_DMA_INT_ENA;
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if (!read)
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bits |= GI_DMA_WRITE;
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ni_tio_set_bits(counter, NITIO_DMA_CFG_REG(cidx), mask, bits);
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break;
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}
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}
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static int ni_tio_input_inttrig(struct comedi_device *dev,
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struct comedi_subdevice *s,
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unsigned int trig_num)
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{
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struct ni_gpct *counter = s->private;
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struct comedi_cmd *cmd = &s->async->cmd;
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unsigned long flags;
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int ret = 0;
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if (trig_num != cmd->start_arg)
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return -EINVAL;
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spin_lock_irqsave(&counter->lock, flags);
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if (counter->mite_chan)
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mite_dma_arm(counter->mite_chan);
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else
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ret = -EIO;
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spin_unlock_irqrestore(&counter->lock, flags);
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if (ret < 0)
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return ret;
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ret = ni_tio_arm(counter, true, NI_GPCT_ARM_IMMEDIATE);
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s->async->inttrig = NULL;
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return ret;
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}
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static int ni_tio_input_cmd(struct comedi_subdevice *s)
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{
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struct ni_gpct *counter = s->private;
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struct ni_gpct_device *counter_dev = counter->counter_dev;
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unsigned int cidx = counter->counter_index;
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struct comedi_async *async = s->async;
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struct comedi_cmd *cmd = &async->cmd;
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int ret = 0;
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/* write alloc the entire buffer */
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comedi_buf_write_alloc(s, async->prealloc_bufsz);
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counter->mite_chan->dir = COMEDI_INPUT;
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switch (counter_dev->variant) {
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case ni_gpct_variant_m_series:
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case ni_gpct_variant_660x:
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mite_prep_dma(counter->mite_chan, 32, 32);
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break;
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case ni_gpct_variant_e_series:
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mite_prep_dma(counter->mite_chan, 16, 32);
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break;
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}
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ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_SAVE_TRACE, 0);
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ni_tio_configure_dma(counter, true, true);
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if (cmd->start_src == TRIG_INT) {
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async->inttrig = &ni_tio_input_inttrig;
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} else { /* TRIG_NOW || TRIG_EXT || TRIG_OTHER */
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async->inttrig = NULL;
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mite_dma_arm(counter->mite_chan);
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if (cmd->start_src == TRIG_NOW)
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ret = ni_tio_arm(counter, true, NI_GPCT_ARM_IMMEDIATE);
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else if (cmd->start_src == TRIG_EXT)
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ret = ni_tio_arm(counter, true, cmd->start_arg);
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}
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return ret;
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}
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static int ni_tio_output_cmd(struct comedi_subdevice *s)
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{
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struct ni_gpct *counter = s->private;
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dev_err(counter->counter_dev->dev->class_dev,
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"output commands not yet implemented.\n");
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return -ENOTSUPP;
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}
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static int ni_tio_cmd_setup(struct comedi_subdevice *s)
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{
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struct comedi_cmd *cmd = &s->async->cmd;
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struct ni_gpct *counter = s->private;
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unsigned int cidx = counter->counter_index;
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int set_gate_source = 0;
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unsigned int gate_source;
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int retval = 0;
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if (cmd->scan_begin_src == TRIG_EXT) {
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set_gate_source = 1;
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gate_source = cmd->scan_begin_arg;
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} else if (cmd->convert_src == TRIG_EXT) {
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set_gate_source = 1;
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gate_source = cmd->convert_arg;
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}
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if (set_gate_source)
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retval = ni_tio_set_gate_src(counter, 0, gate_source);
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if (cmd->flags & CMDF_WAKE_EOS) {
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ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx),
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GI_GATE_INTERRUPT_ENABLE(cidx),
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GI_GATE_INTERRUPT_ENABLE(cidx));
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}
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return retval;
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}
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int ni_tio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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{
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struct ni_gpct *counter = s->private;
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struct comedi_async *async = s->async;
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struct comedi_cmd *cmd = &async->cmd;
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int retval = 0;
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unsigned long flags;
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spin_lock_irqsave(&counter->lock, flags);
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if (!counter->mite_chan) {
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dev_err(counter->counter_dev->dev->class_dev,
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"commands only supported with DMA. ");
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dev_err(counter->counter_dev->dev->class_dev,
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"Interrupt-driven commands not yet implemented.\n");
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retval = -EIO;
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} else {
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retval = ni_tio_cmd_setup(s);
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if (retval == 0) {
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if (cmd->flags & CMDF_WRITE)
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retval = ni_tio_output_cmd(s);
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else
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retval = ni_tio_input_cmd(s);
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}
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}
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spin_unlock_irqrestore(&counter->lock, flags);
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return retval;
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}
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EXPORT_SYMBOL_GPL(ni_tio_cmd);
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int ni_tio_cmdtest(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_cmd *cmd)
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{
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struct ni_gpct *counter = s->private;
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int err = 0;
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unsigned int sources;
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/* Step 1 : check if triggers are trivially valid */
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sources = TRIG_NOW | TRIG_INT | TRIG_OTHER;
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if (ni_tio_counting_mode_registers_present(counter->counter_dev))
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sources |= TRIG_EXT;
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err |= comedi_check_trigger_src(&cmd->start_src, sources);
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err |= comedi_check_trigger_src(&cmd->scan_begin_src,
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TRIG_FOLLOW | TRIG_EXT | TRIG_OTHER);
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err |= comedi_check_trigger_src(&cmd->convert_src,
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TRIG_NOW | TRIG_EXT | TRIG_OTHER);
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err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
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err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
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if (err)
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return 1;
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/* Step 2a : make sure trigger sources are unique */
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err |= comedi_check_trigger_is_unique(cmd->start_src);
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err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
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err |= comedi_check_trigger_is_unique(cmd->convert_src);
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/* Step 2b : and mutually compatible */
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if (cmd->convert_src != TRIG_NOW && cmd->scan_begin_src != TRIG_FOLLOW)
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err |= -EINVAL;
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if (err)
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return 2;
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/* Step 3: check if arguments are trivially valid */
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switch (cmd->start_src) {
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case TRIG_NOW:
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case TRIG_INT:
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case TRIG_OTHER:
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err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
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break;
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case TRIG_EXT:
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/* start_arg is the start_trigger passed to ni_tio_arm() */
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break;
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}
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if (cmd->scan_begin_src != TRIG_EXT)
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err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
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if (cmd->convert_src != TRIG_EXT)
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err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
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err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
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cmd->chanlist_len);
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err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
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if (err)
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return 3;
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/* Step 4: fix up any arguments */
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/* Step 5: check channel list if it exists */
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return 0;
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}
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EXPORT_SYMBOL_GPL(ni_tio_cmdtest);
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int ni_tio_cancel(struct ni_gpct *counter)
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{
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unsigned int cidx = counter->counter_index;
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unsigned long flags;
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ni_tio_arm(counter, false, 0);
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spin_lock_irqsave(&counter->lock, flags);
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if (counter->mite_chan)
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mite_dma_disarm(counter->mite_chan);
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spin_unlock_irqrestore(&counter->lock, flags);
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ni_tio_configure_dma(counter, false, false);
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ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx),
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GI_GATE_INTERRUPT_ENABLE(cidx), 0x0);
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return 0;
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}
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EXPORT_SYMBOL_GPL(ni_tio_cancel);
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static int should_ack_gate(struct ni_gpct *counter)
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{
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unsigned long flags;
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int retval = 0;
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switch (counter->counter_dev->variant) {
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case ni_gpct_variant_m_series:
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case ni_gpct_variant_660x:
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/*
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* not sure if 660x really supports gate interrupts
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* (the bits are not listed in register-level manual)
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*/
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return 1;
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case ni_gpct_variant_e_series:
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/*
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* During buffered input counter operation for e-series,
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* the gate interrupt is acked automatically by the dma
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* controller, due to the Gi_Read/Write_Acknowledges_IRQ
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* bits in the input select register.
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*/
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spin_lock_irqsave(&counter->lock, flags);
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{
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if (!counter->mite_chan ||
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counter->mite_chan->dir != COMEDI_INPUT ||
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(mite_done(counter->mite_chan))) {
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retval = 1;
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}
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}
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spin_unlock_irqrestore(&counter->lock, flags);
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break;
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}
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return retval;
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}
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static void ni_tio_acknowledge_and_confirm(struct ni_gpct *counter,
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int *gate_error,
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int *tc_error,
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int *perm_stale_data)
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{
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unsigned int cidx = counter->counter_index;
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const unsigned short gxx_status = ni_tio_read(counter,
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NITIO_SHARED_STATUS_REG(cidx));
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const unsigned short gi_status = ni_tio_read(counter,
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NITIO_STATUS_REG(cidx));
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unsigned int ack = 0;
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if (gate_error)
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*gate_error = 0;
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if (tc_error)
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*tc_error = 0;
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if (perm_stale_data)
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*perm_stale_data = 0;
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if (gxx_status & GI_GATE_ERROR(cidx)) {
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ack |= GI_GATE_ERROR_CONFIRM(cidx);
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if (gate_error) {
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/*
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* 660x don't support automatic acknowledgment
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* of gate interrupt via dma read/write
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* and report bogus gate errors
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*/
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if (counter->counter_dev->variant !=
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ni_gpct_variant_660x)
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*gate_error = 1;
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}
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}
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if (gxx_status & GI_TC_ERROR(cidx)) {
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ack |= GI_TC_ERROR_CONFIRM(cidx);
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if (tc_error)
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*tc_error = 1;
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}
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if (gi_status & GI_TC)
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ack |= GI_TC_INTERRUPT_ACK;
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if (gi_status & GI_GATE_INTERRUPT) {
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if (should_ack_gate(counter))
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ack |= GI_GATE_INTERRUPT_ACK;
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}
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if (ack)
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ni_tio_write(counter, ack, NITIO_INT_ACK_REG(cidx));
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if (ni_tio_get_soft_copy(counter, NITIO_MODE_REG(cidx)) &
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GI_LOADING_ON_GATE) {
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if (ni_tio_read(counter, NITIO_STATUS2_REG(cidx)) &
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GI_PERMANENT_STALE(cidx)) {
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dev_info(counter->counter_dev->dev->class_dev,
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"%s: Gi_Permanent_Stale_Data detected.\n",
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__func__);
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if (perm_stale_data)
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*perm_stale_data = 1;
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}
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}
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}
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void ni_tio_acknowledge(struct ni_gpct *counter)
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{
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ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL);
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}
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EXPORT_SYMBOL_GPL(ni_tio_acknowledge);
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void ni_tio_handle_interrupt(struct ni_gpct *counter,
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struct comedi_subdevice *s)
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{
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unsigned int cidx = counter->counter_index;
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unsigned long flags;
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int gate_error;
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int tc_error;
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int perm_stale_data;
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ni_tio_acknowledge_and_confirm(counter, &gate_error, &tc_error,
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&perm_stale_data);
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if (gate_error) {
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dev_notice(counter->counter_dev->dev->class_dev,
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"%s: Gi_Gate_Error detected.\n", __func__);
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s->async->events |= COMEDI_CB_OVERFLOW;
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}
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if (perm_stale_data)
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s->async->events |= COMEDI_CB_ERROR;
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switch (counter->counter_dev->variant) {
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case ni_gpct_variant_m_series:
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case ni_gpct_variant_660x:
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if (ni_tio_read(counter, NITIO_DMA_STATUS_REG(cidx)) &
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GI_DRQ_ERROR) {
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dev_notice(counter->counter_dev->dev->class_dev,
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"%s: Gi_DRQ_Error detected.\n", __func__);
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s->async->events |= COMEDI_CB_OVERFLOW;
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}
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break;
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case ni_gpct_variant_e_series:
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break;
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}
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spin_lock_irqsave(&counter->lock, flags);
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if (counter->mite_chan)
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mite_ack_linkc(counter->mite_chan, s, true);
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spin_unlock_irqrestore(&counter->lock, flags);
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}
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EXPORT_SYMBOL_GPL(ni_tio_handle_interrupt);
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void ni_tio_set_mite_channel(struct ni_gpct *counter,
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struct mite_channel *mite_chan)
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{
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unsigned long flags;
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spin_lock_irqsave(&counter->lock, flags);
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counter->mite_chan = mite_chan;
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spin_unlock_irqrestore(&counter->lock, flags);
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}
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EXPORT_SYMBOL_GPL(ni_tio_set_mite_channel);
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static int __init ni_tiocmd_init_module(void)
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{
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return 0;
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}
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module_init(ni_tiocmd_init_module);
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static void __exit ni_tiocmd_cleanup_module(void)
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{
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}
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module_exit(ni_tiocmd_cleanup_module);
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MODULE_AUTHOR("Comedi <comedi@comedi.org>");
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MODULE_DESCRIPTION("Comedi command support for NI general-purpose counters");
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MODULE_LICENSE("GPL");
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