// SPDX-License-Identifier: GPL-2.0
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/*
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* comedi/drivers/adv_pci_dio.c
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*
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* Author: Michal Dobes <dobes@tesnet.cz>
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*
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* Hardware driver for Advantech PCI DIO cards.
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*/
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/*
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* Driver: adv_pci_dio
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* Description: Advantech Digital I/O Cards
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* Devices: [Advantech] PCI-1730 (adv_pci_dio), PCI-1733,
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* PCI-1734, PCI-1735U, PCI-1736UP, PCI-1739U, PCI-1750,
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* PCI-1751, PCI-1752, PCI-1753, PCI-1753+PCI-1753E,
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* PCI-1754, PCI-1756, PCI-1761, PCI-1762
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* Author: Michal Dobes <dobes@tesnet.cz>
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* Updated: Fri, 25 Aug 2017 07:23:06 +0300
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* Status: untested
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*
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* Configuration Options: not applicable, uses PCI auto config
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*/
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#include <linux/module.h>
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#include <linux/delay.h>
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#include "../comedi_pci.h"
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#include "8255.h"
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#include "comedi_8254.h"
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/*
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* Register offset definitions
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*/
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/* PCI-1730, PCI-1733, PCI-1736 interrupt control registers */
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#define PCI173X_INT_EN_REG 0x08 /* R/W: enable/disable */
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#define PCI173X_INT_RF_REG 0x0c /* R/W: falling/rising edge */
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#define PCI173X_INT_CLR_REG 0x10 /* R/W: clear */
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/* PCI-1739U, PCI-1750, PCI1751 interrupt control registers */
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#define PCI1750_INT_REG 0x20 /* R/W: status/control */
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/* PCI-1753, PCI-1753E interrupt control registers */
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#define PCI1753_INT_REG(x) (0x10 + (x)) /* R/W: control group 0 to 3 */
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#define PCI1753E_INT_REG(x) (0x30 + (x)) /* R/W: control group 0 to 3 */
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/* PCI-1754, PCI-1756 interrupt control registers */
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#define PCI1754_INT_REG(x) (0x08 + (x) * 2) /* R/W: control group 0 to 3 */
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/* PCI-1752, PCI-1756 special registers */
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#define PCI1752_CFC_REG 0x12 /* R/W: channel freeze function */
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/* PCI-1761 interrupt control registers */
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#define PCI1761_INT_EN_REG 0x03 /* R/W: enable/disable interrupts */
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#define PCI1761_INT_RF_REG 0x04 /* R/W: falling/rising edge */
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#define PCI1761_INT_CLR_REG 0x05 /* R/W: clear interrupts */
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/* PCI-1762 interrupt control registers */
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#define PCI1762_INT_REG 0x06 /* R/W: status/control */
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/* maximum number of subdevice descriptions in the boardinfo */
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#define PCI_DIO_MAX_DI_SUBDEVS 2 /* 2 x 8/16/32 input channels max */
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#define PCI_DIO_MAX_DO_SUBDEVS 2 /* 2 x 8/16/32 output channels max */
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#define PCI_DIO_MAX_DIO_SUBDEVG 2 /* 2 x any number of 8255 devices max */
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enum pci_dio_boardid {
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TYPE_PCI1730,
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TYPE_PCI1733,
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TYPE_PCI1734,
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TYPE_PCI1735,
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TYPE_PCI1736,
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TYPE_PCI1739,
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TYPE_PCI1750,
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TYPE_PCI1751,
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TYPE_PCI1752,
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TYPE_PCI1753,
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TYPE_PCI1753E,
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TYPE_PCI1754,
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TYPE_PCI1756,
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TYPE_PCI1761,
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TYPE_PCI1762
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};
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struct diosubd_data {
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int chans; /* num of chans or 8255 devices */
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unsigned long addr; /* PCI address ofset */
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};
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struct dio_boardtype {
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const char *name; /* board name */
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int nsubdevs;
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struct diosubd_data sdi[PCI_DIO_MAX_DI_SUBDEVS];
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struct diosubd_data sdo[PCI_DIO_MAX_DO_SUBDEVS];
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struct diosubd_data sdio[PCI_DIO_MAX_DIO_SUBDEVG];
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unsigned long id_reg;
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unsigned long timer_regbase;
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unsigned int is_16bit:1;
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};
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static const struct dio_boardtype boardtypes[] = {
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[TYPE_PCI1730] = {
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.name = "pci1730",
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.nsubdevs = 5,
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.sdi[0] = { 16, 0x02, }, /* DI 0-15 */
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.sdi[1] = { 16, 0x00, }, /* ISO DI 0-15 */
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.sdo[0] = { 16, 0x02, }, /* DO 0-15 */
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.sdo[1] = { 16, 0x00, }, /* ISO DO 0-15 */
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.id_reg = 0x04,
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},
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[TYPE_PCI1733] = {
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.name = "pci1733",
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.nsubdevs = 2,
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.sdi[1] = { 32, 0x00, }, /* ISO DI 0-31 */
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.id_reg = 0x04,
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},
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[TYPE_PCI1734] = {
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.name = "pci1734",
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.nsubdevs = 2,
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.sdo[1] = { 32, 0x00, }, /* ISO DO 0-31 */
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.id_reg = 0x04,
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},
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[TYPE_PCI1735] = {
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.name = "pci1735",
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.nsubdevs = 4,
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.sdi[0] = { 32, 0x00, }, /* DI 0-31 */
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.sdo[0] = { 32, 0x00, }, /* DO 0-31 */
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.id_reg = 0x08,
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.timer_regbase = 0x04,
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},
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[TYPE_PCI1736] = {
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.name = "pci1736",
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.nsubdevs = 3,
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.sdi[1] = { 16, 0x00, }, /* ISO DI 0-15 */
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.sdo[1] = { 16, 0x00, }, /* ISO DO 0-15 */
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.id_reg = 0x04,
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},
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[TYPE_PCI1739] = {
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.name = "pci1739",
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.nsubdevs = 3,
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.sdio[0] = { 2, 0x00, }, /* 8255 DIO */
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.id_reg = 0x08,
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},
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[TYPE_PCI1750] = {
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.name = "pci1750",
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.nsubdevs = 2,
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.sdi[1] = { 16, 0x00, }, /* ISO DI 0-15 */
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.sdo[1] = { 16, 0x00, }, /* ISO DO 0-15 */
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},
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[TYPE_PCI1751] = {
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.name = "pci1751",
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.nsubdevs = 3,
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.sdio[0] = { 2, 0x00, }, /* 8255 DIO */
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.timer_regbase = 0x18,
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},
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[TYPE_PCI1752] = {
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.name = "pci1752",
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.nsubdevs = 3,
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.sdo[0] = { 32, 0x00, }, /* DO 0-31 */
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.sdo[1] = { 32, 0x04, }, /* DO 32-63 */
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.id_reg = 0x10,
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.is_16bit = 1,
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},
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[TYPE_PCI1753] = {
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.name = "pci1753",
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.nsubdevs = 4,
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.sdio[0] = { 4, 0x00, }, /* 8255 DIO */
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},
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[TYPE_PCI1753E] = {
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.name = "pci1753e",
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.nsubdevs = 8,
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.sdio[0] = { 4, 0x00, }, /* 8255 DIO */
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.sdio[1] = { 4, 0x20, }, /* 8255 DIO */
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},
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[TYPE_PCI1754] = {
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.name = "pci1754",
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.nsubdevs = 3,
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.sdi[0] = { 32, 0x00, }, /* DI 0-31 */
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.sdi[1] = { 32, 0x04, }, /* DI 32-63 */
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.id_reg = 0x10,
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.is_16bit = 1,
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},
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[TYPE_PCI1756] = {
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.name = "pci1756",
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.nsubdevs = 3,
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.sdi[1] = { 32, 0x00, }, /* DI 0-31 */
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.sdo[1] = { 32, 0x04, }, /* DO 0-31 */
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.id_reg = 0x10,
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.is_16bit = 1,
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},
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[TYPE_PCI1761] = {
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.name = "pci1761",
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.nsubdevs = 3,
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.sdi[1] = { 8, 0x01 }, /* ISO DI 0-7 */
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.sdo[1] = { 8, 0x00 }, /* RELAY DO 0-7 */
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.id_reg = 0x02,
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},
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[TYPE_PCI1762] = {
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.name = "pci1762",
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.nsubdevs = 3,
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.sdi[1] = { 16, 0x02, }, /* ISO DI 0-15 */
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.sdo[1] = { 16, 0x00, }, /* ISO DO 0-15 */
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.id_reg = 0x04,
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.is_16bit = 1,
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},
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};
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static int pci_dio_insn_bits_di_b(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn,
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unsigned int *data)
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{
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unsigned long reg = (unsigned long)s->private;
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unsigned long iobase = dev->iobase + reg;
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data[1] = inb(iobase);
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if (s->n_chan > 8)
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data[1] |= (inb(iobase + 1) << 8);
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if (s->n_chan > 16)
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data[1] |= (inb(iobase + 2) << 16);
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if (s->n_chan > 24)
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data[1] |= (inb(iobase + 3) << 24);
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return insn->n;
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}
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static int pci_dio_insn_bits_di_w(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn,
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unsigned int *data)
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{
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unsigned long reg = (unsigned long)s->private;
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unsigned long iobase = dev->iobase + reg;
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data[1] = inw(iobase);
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if (s->n_chan > 16)
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data[1] |= (inw(iobase + 2) << 16);
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return insn->n;
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}
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static int pci_dio_insn_bits_do_b(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn,
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unsigned int *data)
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{
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unsigned long reg = (unsigned long)s->private;
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unsigned long iobase = dev->iobase + reg;
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if (comedi_dio_update_state(s, data)) {
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outb(s->state & 0xff, iobase);
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if (s->n_chan > 8)
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outb((s->state >> 8) & 0xff, iobase + 1);
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if (s->n_chan > 16)
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outb((s->state >> 16) & 0xff, iobase + 2);
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if (s->n_chan > 24)
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outb((s->state >> 24) & 0xff, iobase + 3);
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}
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data[1] = s->state;
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return insn->n;
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}
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static int pci_dio_insn_bits_do_w(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn,
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unsigned int *data)
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{
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unsigned long reg = (unsigned long)s->private;
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unsigned long iobase = dev->iobase + reg;
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if (comedi_dio_update_state(s, data)) {
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outw(s->state & 0xffff, iobase);
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if (s->n_chan > 16)
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outw((s->state >> 16) & 0xffff, iobase + 2);
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}
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data[1] = s->state;
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return insn->n;
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}
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static int pci_dio_reset(struct comedi_device *dev, unsigned long cardtype)
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{
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/* disable channel freeze function on the PCI-1752/1756 boards */
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if (cardtype == TYPE_PCI1752 || cardtype == TYPE_PCI1756)
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outw(0, dev->iobase + PCI1752_CFC_REG);
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/* disable and clear interrupts */
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switch (cardtype) {
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case TYPE_PCI1730:
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case TYPE_PCI1733:
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case TYPE_PCI1736:
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outb(0, dev->iobase + PCI173X_INT_EN_REG);
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outb(0x0f, dev->iobase + PCI173X_INT_CLR_REG);
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outb(0, dev->iobase + PCI173X_INT_RF_REG);
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break;
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case TYPE_PCI1739:
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case TYPE_PCI1750:
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case TYPE_PCI1751:
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outb(0x88, dev->iobase + PCI1750_INT_REG);
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break;
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case TYPE_PCI1753:
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case TYPE_PCI1753E:
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outb(0x88, dev->iobase + PCI1753_INT_REG(0));
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outb(0x80, dev->iobase + PCI1753_INT_REG(1));
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outb(0x80, dev->iobase + PCI1753_INT_REG(2));
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outb(0x80, dev->iobase + PCI1753_INT_REG(3));
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if (cardtype == TYPE_PCI1753E) {
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outb(0x88, dev->iobase + PCI1753E_INT_REG(0));
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outb(0x80, dev->iobase + PCI1753E_INT_REG(1));
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outb(0x80, dev->iobase + PCI1753E_INT_REG(2));
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outb(0x80, dev->iobase + PCI1753E_INT_REG(3));
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}
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break;
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case TYPE_PCI1754:
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case TYPE_PCI1756:
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outw(0x08, dev->iobase + PCI1754_INT_REG(0));
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outw(0x08, dev->iobase + PCI1754_INT_REG(1));
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if (cardtype == TYPE_PCI1754) {
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outw(0x08, dev->iobase + PCI1754_INT_REG(2));
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outw(0x08, dev->iobase + PCI1754_INT_REG(3));
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}
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break;
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case TYPE_PCI1761:
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/* disable interrupts */
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outb(0, dev->iobase + PCI1761_INT_EN_REG);
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/* clear interrupts */
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outb(0xff, dev->iobase + PCI1761_INT_CLR_REG);
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/* set rising edge trigger */
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outb(0, dev->iobase + PCI1761_INT_RF_REG);
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break;
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case TYPE_PCI1762:
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outw(0x0101, dev->iobase + PCI1762_INT_REG);
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break;
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default:
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break;
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}
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return 0;
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}
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static int pci_dio_auto_attach(struct comedi_device *dev,
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unsigned long context)
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{
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struct pci_dev *pcidev = comedi_to_pci_dev(dev);
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const struct dio_boardtype *board = NULL;
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const struct diosubd_data *d;
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struct comedi_subdevice *s;
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int ret, subdev, i, j;
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if (context < ARRAY_SIZE(boardtypes))
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board = &boardtypes[context];
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if (!board)
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return -ENODEV;
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dev->board_ptr = board;
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dev->board_name = board->name;
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ret = comedi_pci_enable(dev);
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if (ret)
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return ret;
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if (context == TYPE_PCI1736)
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dev->iobase = pci_resource_start(pcidev, 0);
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else
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dev->iobase = pci_resource_start(pcidev, 2);
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pci_dio_reset(dev, context);
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ret = comedi_alloc_subdevices(dev, board->nsubdevs);
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if (ret)
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return ret;
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subdev = 0;
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for (i = 0; i < PCI_DIO_MAX_DI_SUBDEVS; i++) {
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d = &board->sdi[i];
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if (d->chans) {
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s = &dev->subdevices[subdev++];
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s->type = COMEDI_SUBD_DI;
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s->subdev_flags = SDF_READABLE;
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s->n_chan = d->chans;
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s->maxdata = 1;
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s->range_table = &range_digital;
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s->insn_bits = board->is_16bit
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? pci_dio_insn_bits_di_w
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: pci_dio_insn_bits_di_b;
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s->private = (void *)d->addr;
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}
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}
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for (i = 0; i < PCI_DIO_MAX_DO_SUBDEVS; i++) {
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d = &board->sdo[i];
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if (d->chans) {
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s = &dev->subdevices[subdev++];
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s->type = COMEDI_SUBD_DO;
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s->subdev_flags = SDF_WRITABLE;
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s->n_chan = d->chans;
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s->maxdata = 1;
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s->range_table = &range_digital;
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s->insn_bits = board->is_16bit
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? pci_dio_insn_bits_do_w
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: pci_dio_insn_bits_do_b;
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s->private = (void *)d->addr;
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/* reset all outputs to 0 */
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if (board->is_16bit) {
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outw(0, dev->iobase + d->addr);
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if (s->n_chan > 16)
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outw(0, dev->iobase + d->addr + 2);
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} else {
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outb(0, dev->iobase + d->addr);
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if (s->n_chan > 8)
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outb(0, dev->iobase + d->addr + 1);
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if (s->n_chan > 16)
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outb(0, dev->iobase + d->addr + 2);
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if (s->n_chan > 24)
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outb(0, dev->iobase + d->addr + 3);
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}
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}
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}
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for (i = 0; i < PCI_DIO_MAX_DIO_SUBDEVG; i++) {
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d = &board->sdio[i];
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for (j = 0; j < d->chans; j++) {
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s = &dev->subdevices[subdev++];
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ret = subdev_8255_init(dev, s, NULL,
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d->addr + j * I8255_SIZE);
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if (ret)
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return ret;
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}
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}
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if (board->id_reg) {
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s = &dev->subdevices[subdev++];
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s->type = COMEDI_SUBD_DI;
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s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
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s->n_chan = 4;
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s->maxdata = 1;
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s->range_table = &range_digital;
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s->insn_bits = board->is_16bit ? pci_dio_insn_bits_di_w
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: pci_dio_insn_bits_di_b;
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s->private = (void *)board->id_reg;
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}
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if (board->timer_regbase) {
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s = &dev->subdevices[subdev++];
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dev->pacer = comedi_8254_init(dev->iobase +
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board->timer_regbase,
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0, I8254_IO8, 0);
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if (!dev->pacer)
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return -ENOMEM;
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comedi_8254_subdevice_init(s, dev->pacer);
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}
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return 0;
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}
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static struct comedi_driver adv_pci_dio_driver = {
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.driver_name = "adv_pci_dio",
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.module = THIS_MODULE,
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.auto_attach = pci_dio_auto_attach,
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.detach = comedi_pci_detach,
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};
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static unsigned long pci_dio_override_cardtype(struct pci_dev *pcidev,
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unsigned long cardtype)
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{
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/*
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* Change cardtype from TYPE_PCI1753 to TYPE_PCI1753E if expansion
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* board available. Need to enable PCI device and request the main
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* registers PCI BAR temporarily to perform the test.
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*/
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if (cardtype != TYPE_PCI1753)
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return cardtype;
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if (pci_enable_device(pcidev) < 0)
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return cardtype;
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if (pci_request_region(pcidev, 2, "adv_pci_dio") == 0) {
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/*
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* This test is based on Advantech's "advdaq" driver source
|
* (which declares its module licence as "GPL" although the
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* driver source does not include a "COPYING" file).
|
*/
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unsigned long reg = pci_resource_start(pcidev, 2) + 53;
|
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outb(0x05, reg);
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if ((inb(reg) & 0x07) == 0x02) {
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outb(0x02, reg);
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if ((inb(reg) & 0x07) == 0x05)
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cardtype = TYPE_PCI1753E;
|
}
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pci_release_region(pcidev, 2);
|
}
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pci_disable_device(pcidev);
|
return cardtype;
|
}
|
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static int adv_pci_dio_pci_probe(struct pci_dev *dev,
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const struct pci_device_id *id)
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{
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unsigned long cardtype;
|
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cardtype = pci_dio_override_cardtype(dev, id->driver_data);
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return comedi_pci_auto_config(dev, &adv_pci_dio_driver, cardtype);
|
}
|
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static const struct pci_device_id adv_pci_dio_pci_table[] = {
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{ PCI_VDEVICE(ADVANTECH, 0x1730), TYPE_PCI1730 },
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{ PCI_VDEVICE(ADVANTECH, 0x1733), TYPE_PCI1733 },
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{ PCI_VDEVICE(ADVANTECH, 0x1734), TYPE_PCI1734 },
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{ PCI_VDEVICE(ADVANTECH, 0x1735), TYPE_PCI1735 },
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{ PCI_VDEVICE(ADVANTECH, 0x1736), TYPE_PCI1736 },
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{ PCI_VDEVICE(ADVANTECH, 0x1739), TYPE_PCI1739 },
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{ PCI_VDEVICE(ADVANTECH, 0x1750), TYPE_PCI1750 },
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{ PCI_VDEVICE(ADVANTECH, 0x1751), TYPE_PCI1751 },
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{ PCI_VDEVICE(ADVANTECH, 0x1752), TYPE_PCI1752 },
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{ PCI_VDEVICE(ADVANTECH, 0x1753), TYPE_PCI1753 },
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{ PCI_VDEVICE(ADVANTECH, 0x1754), TYPE_PCI1754 },
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{ PCI_VDEVICE(ADVANTECH, 0x1756), TYPE_PCI1756 },
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{ PCI_VDEVICE(ADVANTECH, 0x1761), TYPE_PCI1761 },
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{ PCI_VDEVICE(ADVANTECH, 0x1762), TYPE_PCI1762 },
|
{ 0 }
|
};
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MODULE_DEVICE_TABLE(pci, adv_pci_dio_pci_table);
|
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static struct pci_driver adv_pci_dio_pci_driver = {
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.name = "adv_pci_dio",
|
.id_table = adv_pci_dio_pci_table,
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.probe = adv_pci_dio_pci_probe,
|
.remove = comedi_pci_auto_unconfig,
|
};
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module_comedi_pci_driver(adv_pci_dio_driver, adv_pci_dio_pci_driver);
|
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MODULE_AUTHOR("Comedi http://www.comedi.org");
|
MODULE_DESCRIPTION("Comedi driver for Advantech Digital I/O Cards");
|
MODULE_LICENSE("GPL");
|
