/*
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* Hisilicon Reset Controller Driver
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*
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* Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include "reset.h"
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#define HISI_RESET_BIT_MASK 0x1f
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#define HISI_RESET_OFFSET_SHIFT 8
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#define HISI_RESET_OFFSET_MASK 0xffff00
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struct hisi_reset_controller {
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spinlock_t lock;
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void __iomem *membase;
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struct reset_controller_dev rcdev;
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};
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#define to_hisi_reset_controller(rcdev) \
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container_of(rcdev, struct hisi_reset_controller, rcdev)
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static int hisi_reset_of_xlate(struct reset_controller_dev *rcdev,
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const struct of_phandle_args *reset_spec)
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{
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u32 offset;
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u8 bit;
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offset = (reset_spec->args[0] << HISI_RESET_OFFSET_SHIFT)
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& HISI_RESET_OFFSET_MASK;
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bit = reset_spec->args[1] & HISI_RESET_BIT_MASK;
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return (offset | bit);
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}
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static int hisi_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct hisi_reset_controller *rstc = to_hisi_reset_controller(rcdev);
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unsigned long flags;
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u32 offset, reg;
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u8 bit;
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offset = (id & HISI_RESET_OFFSET_MASK) >> HISI_RESET_OFFSET_SHIFT;
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bit = id & HISI_RESET_BIT_MASK;
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spin_lock_irqsave(&rstc->lock, flags);
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reg = readl(rstc->membase + offset);
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writel(reg | BIT(bit), rstc->membase + offset);
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spin_unlock_irqrestore(&rstc->lock, flags);
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return 0;
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}
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static int hisi_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct hisi_reset_controller *rstc = to_hisi_reset_controller(rcdev);
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unsigned long flags;
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u32 offset, reg;
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u8 bit;
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offset = (id & HISI_RESET_OFFSET_MASK) >> HISI_RESET_OFFSET_SHIFT;
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bit = id & HISI_RESET_BIT_MASK;
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spin_lock_irqsave(&rstc->lock, flags);
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reg = readl(rstc->membase + offset);
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writel(reg & ~BIT(bit), rstc->membase + offset);
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spin_unlock_irqrestore(&rstc->lock, flags);
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return 0;
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}
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static const struct reset_control_ops hisi_reset_ops = {
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.assert = hisi_reset_assert,
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.deassert = hisi_reset_deassert,
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};
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struct hisi_reset_controller *hisi_reset_init(struct platform_device *pdev)
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{
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struct hisi_reset_controller *rstc;
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struct resource *res;
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rstc = devm_kmalloc(&pdev->dev, sizeof(*rstc), GFP_KERNEL);
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if (!rstc)
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return NULL;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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rstc->membase = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(rstc->membase))
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return NULL;
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spin_lock_init(&rstc->lock);
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rstc->rcdev.owner = THIS_MODULE;
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rstc->rcdev.ops = &hisi_reset_ops;
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rstc->rcdev.of_node = pdev->dev.of_node;
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rstc->rcdev.of_reset_n_cells = 2;
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rstc->rcdev.of_xlate = hisi_reset_of_xlate;
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reset_controller_register(&rstc->rcdev);
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return rstc;
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}
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EXPORT_SYMBOL_GPL(hisi_reset_init);
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void hisi_reset_exit(struct hisi_reset_controller *rstc)
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{
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reset_controller_unregister(&rstc->rcdev);
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}
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EXPORT_SYMBOL_GPL(hisi_reset_exit);
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