/*
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* Copyright (C) 2012 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _ASM_RISCV_MMU_CONTEXT_H
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#define _ASM_RISCV_MMU_CONTEXT_H
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#include <linux/mm_types.h>
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#include <asm-generic/mm_hooks.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <asm/tlbflush.h>
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#include <asm/cacheflush.h>
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static inline void enter_lazy_tlb(struct mm_struct *mm,
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struct task_struct *task)
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{
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}
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/* Initialize context-related info for a new mm_struct */
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static inline int init_new_context(struct task_struct *task,
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struct mm_struct *mm)
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{
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return 0;
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}
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static inline void destroy_context(struct mm_struct *mm)
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{
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}
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/*
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* When necessary, performs a deferred icache flush for the given MM context,
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* on the local CPU. RISC-V has no direct mechanism for instruction cache
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* shoot downs, so instead we send an IPI that informs the remote harts they
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* need to flush their local instruction caches. To avoid pathologically slow
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* behavior in a common case (a bunch of single-hart processes on a many-hart
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* machine, ie 'make -j') we avoid the IPIs for harts that are not currently
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* executing a MM context and instead schedule a deferred local instruction
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* cache flush to be performed before execution resumes on each hart. This
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* actually performs that local instruction cache flush, which implicitly only
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* refers to the current hart.
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*/
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static inline void flush_icache_deferred(struct mm_struct *mm)
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{
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#ifdef CONFIG_SMP
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unsigned int cpu = smp_processor_id();
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cpumask_t *mask = &mm->context.icache_stale_mask;
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if (cpumask_test_cpu(cpu, mask)) {
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cpumask_clear_cpu(cpu, mask);
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/*
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* Ensure the remote hart's writes are visible to this hart.
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* This pairs with a barrier in flush_icache_mm.
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*/
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smp_mb();
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local_flush_icache_all();
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}
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#endif
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}
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static inline void switch_mm(struct mm_struct *prev,
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struct mm_struct *next, struct task_struct *task)
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{
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if (likely(prev != next)) {
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/*
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* Mark the current MM context as inactive, and the next as
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* active. This is at least used by the icache flushing
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* routines in order to determine who should
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*/
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unsigned int cpu = smp_processor_id();
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cpumask_clear_cpu(cpu, mm_cpumask(prev));
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cpumask_set_cpu(cpu, mm_cpumask(next));
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/*
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* Use the old spbtr name instead of using the current satp
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* name to support binutils 2.29 which doesn't know about the
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* privileged ISA 1.10 yet.
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*/
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csr_write(sptbr, virt_to_pfn(next->pgd) | SATP_MODE);
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local_flush_tlb_all();
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flush_icache_deferred(next);
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}
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}
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static inline void activate_mm(struct mm_struct *prev,
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struct mm_struct *next)
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{
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switch_mm(prev, next, NULL);
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}
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static inline void deactivate_mm(struct task_struct *task,
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struct mm_struct *mm)
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{
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}
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#endif /* _ASM_RISCV_MMU_CONTEXT_H */
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