/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Derived from IRIX <sys/SN/SN0/IP27.h>.
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*
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* Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
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* Copyright (C) 1999, 2006 by Ralf Baechle
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*/
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#ifndef _ASM_SN_SN0_IP27_H
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#define _ASM_SN_SN0_IP27_H
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#include <asm/mipsregs.h>
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/*
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* Simple definitions for the masks which remove SW bits from pte.
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*/
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#define TLBLO_HWBITSHIFT 0 /* Shift value, for masking */
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#ifndef __ASSEMBLY__
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#define CAUSE_BERRINTR IE_IRQ5
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#define ECCF_CACHE_ERR 0
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#define ECCF_TAGLO 1
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#define ECCF_ECC 2
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#define ECCF_ERROREPC 3
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#define ECCF_PADDR 4
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#define ECCF_SIZE (5 * sizeof(long))
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#endif /* !__ASSEMBLY__ */
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#ifdef __ASSEMBLY__
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/*
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* KL_GET_CPUNUM (similar to EV_GET_SPNUM for EVEREST platform) reads
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* the processor number of the calling processor. The proc parameters
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* must be a register.
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*/
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#define KL_GET_CPUNUM(proc) \
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dli proc, LOCAL_HUB(0); \
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ld proc, PI_CPU_NUM(proc)
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#endif /* __ASSEMBLY__ */
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/*
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* R10000 status register interrupt bit mask usage for IP27.
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*/
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#define SRB_SWTIMO IE_SW0 /* 0x0100 */
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#define SRB_NET IE_SW1 /* 0x0200 */
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#define SRB_DEV0 IE_IRQ0 /* 0x0400 */
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#define SRB_DEV1 IE_IRQ1 /* 0x0800 */
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#define SRB_TIMOCLK IE_IRQ2 /* 0x1000 */
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#define SRB_PROFCLK IE_IRQ3 /* 0x2000 */
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#define SRB_ERR IE_IRQ4 /* 0x4000 */
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#define SRB_SCHEDCLK IE_IRQ5 /* 0x8000 */
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#define SR_IBIT_HI SRB_DEV0
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#define SR_IBIT_PROF SRB_PROFCLK
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#define SRB_SWTIMO_IDX 0
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#define SRB_NET_IDX 1
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#define SRB_DEV0_IDX 2
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#define SRB_DEV1_IDX 3
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#define SRB_TIMOCLK_IDX 4
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#define SRB_PROFCLK_IDX 5
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#define SRB_ERR_IDX 6
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#define SRB_SCHEDCLK_IDX 7
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#define NUM_CAUSE_INTRS 8
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#define SCACHE_LINESIZE 128
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#define SCACHE_LINEMASK (SCACHE_LINESIZE - 1)
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#include <asm/sn/addrs.h>
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#define LED_CYCLE_MASK 0x0f
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#define LED_CYCLE_SHFT 4
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#define SEND_NMI(_nasid, _slice) \
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REMOTE_HUB_S((_nasid), (PI_NMI_A + ((_slice) * PI_NMI_OFFSET)), 1)
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#endif /* _ASM_SN_SN0_IP27_H */
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