1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
| [
| {
| "ArchStdEvent": "L1D_CACHE_RD",
| },
| {
| "ArchStdEvent": "L1D_CACHE_WR",
| },
| {
| "ArchStdEvent": "L1D_CACHE_REFILL_RD",
| },
| {
| "ArchStdEvent": "L1D_CACHE_REFILL_WR",
| },
| {
| "ArchStdEvent": "L1D_TLB_REFILL_RD",
| },
| {
| "ArchStdEvent": "L1D_TLB_REFILL_WR",
| },
| {
| "ArchStdEvent": "L1D_TLB_RD",
| },
| {
| "ArchStdEvent": "L1D_TLB_WR",
| },
| {
| "ArchStdEvent": "BUS_ACCESS_RD",
| },
| {
| "ArchStdEvent": "BUS_ACCESS_WR",
| }
| ]
|
|
