Rockchip Dynamic Memory Controller Driver
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Required properties:
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- compatible: "rockchip,rk3288-dmc", "syscon"
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- rockchip,cru: this driver should access cru regs, so need get cru here
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- rockchip,grf: this driver should access grf regs, so need get grf here
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- rockchip,pmu: this driver should access pmu regs, so need get pmu here
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- rockchip,sgrf: this driver should access sgrf regs, so need get sgrf here
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- rockchip,noc: this driver should access noc regs, so need get noc here
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- reg: dynamic ram protocol controller(PCTL) address and phy controller(PHYCTL) address
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- clock: must include clock specifiers corresponding to entries in the clock-names property.
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- clock-output-names: from common clock binding to override the default output clock name
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Must contain
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pclk_ddrupctl0: support clock for access protocol controller registers of channel 0
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pclk_publ0: support clock for access phy controller registers of channel 0
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pclk_ddrupctl1: support clock for access protocol controller registers of channel 1
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pclk_publ1: support clock for access phy controller registers of channel 1
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arm_clk: for get arm frequency
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-logic-supply: this driver should adjust VDD_LOGIC according to dmc frequency, so need get logic-supply here
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-timings:
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Must contain
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rockchip,odt-disable-freq: if ddr clock frequency low than odt-disable-freq,this driver should disable DDR ODT
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rockchip,dll-disable-freq: if ddr clock frequency low than dll-disable-freq,this driver should disable DDR DLL
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rockchip,sr-enable-freq: if ddr clock frequency high than sr-enable-freq,this driver should enable the automatic self refresh function
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rockchip,pd-enable-freq: if ddr clock frequency high than pd-enable-freq,this driver should enable the automatic power down function
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rockchip,auto-self-refresh-cnt: Self Refresh idle period. Memories are placed into Self-Refresh mode if the NIF is idle in Access state for auto-self-refresh-cnt * 32 * n_clk cycles.The automatic self refresh function is disabled when auto-self-refresh-cnt=0.
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rockchip,auto-power-down-cnt: Power-down idle period. Memories are placed into power-down mode if the NIF is idle for auto-power-down-cnt n_clk cycles.The automatic power down function is disabled when auto-power-down-cnt=0.
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rockchip,ddr-speed-bin: DDR3 type,AC timing parameters from the memory data-sheet
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0.DDR3_800D (5-5-5)
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1.DDR3_800E (6-6-6)
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2.DDR3_1066E (6-6-6)
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3.DDR3_1066F (7-7-7)
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4.DDR3_1066G (8-8-8)
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5.DDR3_1333F (7-7-7)
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6.DDR3_1333G (8-8-8)
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7.DDR3_1333H (9-9-9)
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8.DDR3_1333J (10-10-10)
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9.DDR3_1600G (8-8-8)
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10.DDR3_1600H (9-9-9)
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11.DDR3_1600J (10-10-10)
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12.DDR3_1600K (11-11-11)
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13.DDR3_1866J (10-10-10)
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14.DDR3_1866K (11-11-11)
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15.DDR3_1866L (12-12-12)
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16.DDR3_1866M (13-13-13)
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17.DDR3_2133K (11-11-11)
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18.DDR3_2133L (12-12-12)
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19.DDR3_2133M (13-13-13)
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20.DDR3_2133N (14-14-14)
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21.DDR3_DEFAULT
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rockchip,trcd: tRCD,AC timing parameters from the memory data-sheet
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rockchip,trp: tRP,AC timing parameters from the memory data-sheet
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-rockchip,num-channels: number of SDRAM channels (1 or 2)
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-rockchip,pctl-timing: parameters for the SDRAM setup, in this order:
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togcnt1u
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tinit
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trsth
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togcnt100n
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trefi
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tmrd
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trfc
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trp
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trtw
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tal
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tcl
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tcwl
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tras
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trc
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trcd
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trrd
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trtp
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twr
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twtr
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texsr
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txp
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txpdll
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tzqcs
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tzqcsi
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tdqs
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tcksre
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tcksrx
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tcke
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tmod
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trstl
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tzqcl
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tmrr
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tckesr
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tdpd
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-rockchip,phy-timing: PHY timing information in this order:
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dtpr0
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dtpr1
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dtpr2
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mr0..mr3
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-rockchip,sdram-channel: SDRAM channel information, each 8 bits. Both channels
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will be set up the same. The parameters are in this order:
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rank
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col
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bk
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bw
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dbw
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row_3_4
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cs0_row
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cs1_row
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- rockchip,sdram-params: SDRAM base parameters, in this order:
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NOC timing - value for ddrtiming register
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NOC activate - value for activate register
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ddrconf - value for ddrconf register
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DDR frequency in MHz
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DRAM type (3=DDR3, 6=LPDDR3)
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stride - stride value for soc_con2 register
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odt - 1 to enable DDR ODT, 0 to disable
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Example:
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dmc: dmc@ff610000 {
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compatible = "rockchip,rk3288-dmc", "syscon";
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rockchip,cru = <&cru>;
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rockchip,grf = <&grf>;
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rockchip,pmu = <&pmu>;
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rockchip,sgrf = <&sgrf>;
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rockchip,noc = <&noc>;
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reg = <0xff610000 0x3fc
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0xff620000 0x294
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0xff630000 0x3fc
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0xff640000 0x294>;
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clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
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<&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
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<&cru ARMCLK>;
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clock-names = "pclk_ddrupctl0", "pclk_publ0",
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"pclk_ddrupctl1", "pclk_publ1",
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"arm_clk";
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};
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&dmc {
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logic-supply = <&vdd_logic>;
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timings {
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rockchip,odt-disable-freq = <333000000>;
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rockchip,dll-disable-freq = <333000000>;
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rockchip,sr-enable-freq = <333000000>;
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rockchip,pd-enable-freq = <666000000>;
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rockchip,auto-self-refresh-cnt = <0>;
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rockchip,auto-power-down-cnt = <64>;
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rockchip,ddr-speed-bin = <21>;
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rockchip,trcd = <10>;
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rockchip,trp = <10>;
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};
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rockchip,num-channels = <2>;
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rockchip,pctl-timing = <0x29a 0x1f4 0xc8 0x42 0x4e 0x4 0xea 0xa
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0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
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0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
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0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
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0x5 0x0>;
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rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
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0xa60 0x40 0x10 0x0>;
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rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf>;
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rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
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};
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