/*
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* linux/arch/unicore32/kernel/entry.S
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Copyright (C) 2001-2010 GUAN Xue-tao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Low-level vector interface routines
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/errno.h>
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#include <asm/thread_info.h>
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#include <asm/memory.h>
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#include <asm/unistd.h>
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#include <generated/asm-offsets.h>
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#include "debug-macro.S"
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@
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@ Most of the stack format comes from struct pt_regs, but with
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@ the addition of 8 bytes for storing syscall args 5 and 6.
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@
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#define S_OFF 8
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/*
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* The SWI code relies on the fact that R0 is at the bottom of the stack
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* (due to slow/fast restore user regs).
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*/
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#if S_R0 != 0
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#error "Please fix"
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#endif
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.macro zero_fp
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#ifdef CONFIG_FRAME_POINTER
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mov fp, #0
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#endif
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.endm
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.macro alignment_trap, rtemp
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#ifdef CONFIG_ALIGNMENT_TRAP
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ldw \rtemp, .LCcralign
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ldw \rtemp, [\rtemp]
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movc p0.c1, \rtemp, #0
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#endif
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.endm
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.macro load_user_sp_lr, rd, rtemp, offset = 0
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mov \rtemp, asr
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xor \rtemp, \rtemp, #(PRIV_MODE ^ SUSR_MODE)
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mov.a asr, \rtemp @ switch to the SUSR mode
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ldw sp, [\rd+], #\offset @ load sp_user
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ldw lr, [\rd+], #\offset + 4 @ load lr_user
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xor \rtemp, \rtemp, #(PRIV_MODE ^ SUSR_MODE)
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mov.a asr, \rtemp @ switch back to the PRIV mode
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.endm
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.macro priv_exit, rpsr
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mov.a bsr, \rpsr
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ldm.w (r0 - r15), [sp]+
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ldm.b (r16 - pc), [sp]+ @ load r0 - pc, asr
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.endm
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.macro restore_user_regs, fast = 0, offset = 0
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ldw r1, [sp+], #\offset + S_PSR @ get calling asr
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ldw lr, [sp+], #\offset + S_PC @ get pc
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mov.a bsr, r1 @ save in bsr_priv
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.if \fast
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add sp, sp, #\offset + S_R1 @ r0 is syscall return value
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ldm.w (r1 - r15), [sp]+ @ get calling r1 - r15
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ldur (r16 - lr), [sp]+ @ get calling r16 - lr
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.else
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ldm.w (r0 - r15), [sp]+ @ get calling r0 - r15
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ldur (r16 - lr), [sp]+ @ get calling r16 - lr
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.endif
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nop
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add sp, sp, #S_FRAME_SIZE - S_R16
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mov.a pc, lr @ return
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@ and move bsr_priv into asr
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.endm
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.macro get_thread_info, rd
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mov \rd, sp >> #13
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mov \rd, \rd << #13
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldw \base, =(PKUNITY_INTC_BASE)
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ldw \irqstat, [\base+], #0xC @ INTC_ICIP
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ldw \tmp, [\base+], #0x4 @ INTC_ICMR
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and.a \irqstat, \irqstat, \tmp
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beq 1001f
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cntlz \irqnr, \irqstat
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rsub \irqnr, \irqnr, #31
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1001: /* EQ will be set if no irqs pending */
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.endm
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#ifdef CONFIG_DEBUG_LL
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.macro printreg, reg, temp
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adr \temp, 901f
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stm (r0-r3), [\temp]+
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stw lr, [\temp+], #0x10
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mov r0, \reg
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b.l printhex8
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mov r0, #':'
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b.l printch
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mov r0, pc
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b.l printhex8
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adr r0, 902f
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b.l printascii
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adr \temp, 901f
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ldm (r0-r3), [\temp]+
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ldw lr, [\temp+], #0x10
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b 903f
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901: .word 0, 0, 0, 0, 0 @ r0-r3, lr
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902: .asciz ": epip4d\n"
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.align
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903:
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.endm
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#endif
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/*
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* These are the registers used in the syscall handler, and allow us to
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* have in theory up to 7 arguments to a function - r0 to r6.
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*
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* Note that tbl == why is intentional.
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*
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* We must set at least "tsk" and "why" when calling ret_with_reschedule.
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*/
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scno .req r21 @ syscall number
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tbl .req r22 @ syscall table pointer
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why .req r22 @ Linux syscall (!= 0)
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tsk .req r23 @ current thread_info
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/*
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* Interrupt handling. Preserves r17, r18, r19
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*/
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.macro intr_handler
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1: get_irqnr_and_base r0, r6, r5, lr
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beq 2f
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mov r1, sp
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@
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@ routine called with r0 = irq number, r1 = struct pt_regs *
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@
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adr lr, 1b
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b asm_do_IRQ
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2:
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.endm
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/*
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* PRIV mode handlers
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*/
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.macro priv_entry
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sub sp, sp, #(S_FRAME_SIZE - 4)
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stm (r1 - r15), [sp]+
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add r5, sp, #S_R15
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stm (r16 - r28), [r5]+
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ldm (r1 - r3), [r0]+
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add r5, sp, #S_SP - 4 @ here for interlock avoidance
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mov r4, #-1 @ "" "" "" ""
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add r0, sp, #(S_FRAME_SIZE - 4)
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stw.w r1, [sp+], #-4 @ save the "real" r0 copied
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@ from the exception stack
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mov r1, lr
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@
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@ We are now ready to fill in the remaining blanks on the stack:
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@
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@ r0 - sp_priv
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@ r1 - lr_priv
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@ r2 - lr_<exception>, already fixed up for correct return/restart
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@ r3 - bsr_<exception>
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@ r4 - orig_r0 (see pt_regs definition in ptrace.h)
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@
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stm (r0 - r4), [r5]+
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.endm
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/*
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* User mode handlers
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*
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*/
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.macro user_entry
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sub sp, sp, #S_FRAME_SIZE
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stm (r1 - r15), [sp+]
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add r4, sp, #S_R16
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stm (r16 - r28), [r4]+
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ldm (r1 - r3), [r0]+
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add r0, sp, #S_PC @ here for interlock avoidance
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mov r4, #-1 @ "" "" "" ""
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stw r1, [sp] @ save the "real" r0 copied
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@ from the exception stack
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@
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@ We are now ready to fill in the remaining blanks on the stack:
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@
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@ r2 - lr_<exception>, already fixed up for correct return/restart
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@ r3 - bsr_<exception>
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@ r4 - orig_r0 (see pt_regs definition in ptrace.h)
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@
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@ Also, separately save sp_user and lr_user
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@
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stm (r2 - r4), [r0]+
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stur (sp, lr), [r0-]
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@
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@ Enable the alignment trap while in kernel mode
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@
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alignment_trap r0
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@
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@ Clear FP to mark the first stack frame
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@
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zero_fp
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.endm
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.text
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@
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@ __invalid - generic code for failed exception
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@ (re-entrant version of handlers)
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@
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__invalid:
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sub sp, sp, #S_FRAME_SIZE
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stm (r1 - r15), [sp+]
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add r1, sp, #S_R16
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stm (r16 - r28, sp, lr), [r1]+
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zero_fp
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ldm (r4 - r6), [r0]+
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add r0, sp, #S_PC @ here for interlock avoidance
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mov r7, #-1 @ "" "" "" ""
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stw r4, [sp] @ save preserved r0
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stm (r5 - r7), [r0]+ @ lr_<exception>,
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@ asr_<exception>, "old_r0"
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mov r0, sp
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mov r1, asr
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b bad_mode
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ENDPROC(__invalid)
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.align 5
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__dabt_priv:
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priv_entry
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@
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@ get ready to re-enable interrupts if appropriate
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@
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mov r17, asr
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cand.a r3, #PSR_I_BIT
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bne 1f
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andn r17, r17, #PSR_I_BIT
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1:
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@
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@ Call the processor-specific abort handler:
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@
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@ r2 - aborted context pc
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@ r3 - aborted context asr
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@
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@ The abort handler must return the aborted address in r0, and
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@ the fault status register in r1.
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@
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movc r1, p0.c3, #0 @ get FSR
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movc r0, p0.c4, #0 @ get FAR
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@
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@ set desired INTR state, then call main handler
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@
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mov.a asr, r17
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mov r2, sp
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b.l do_DataAbort
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@
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@ INTRs off again before pulling preserved data off the stack
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@
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disable_irq r0
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@
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@ restore BSR and restart the instruction
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@
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ldw r2, [sp+], #S_PSR
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priv_exit r2 @ return from exception
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ENDPROC(__dabt_priv)
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.align 5
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__intr_priv:
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priv_entry
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intr_handler
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mov r0, #0 @ epip4d
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movc p0.c5, r0, #14
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nop; nop; nop; nop; nop; nop; nop; nop
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ldw r4, [sp+], #S_PSR @ irqs are already disabled
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priv_exit r4 @ return from exception
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ENDPROC(__intr_priv)
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.ltorg
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.align 5
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__extn_priv:
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priv_entry
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mov r0, sp @ struct pt_regs *regs
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mov r1, asr
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b bad_mode @ not supported
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ENDPROC(__extn_priv)
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.align 5
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__pabt_priv:
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priv_entry
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@
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@ re-enable interrupts if appropriate
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@
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mov r17, asr
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cand.a r3, #PSR_I_BIT
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bne 1f
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andn r17, r17, #PSR_I_BIT
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1:
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@
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@ set args, then call main handler
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@
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@ r0 - address of faulting instruction
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@ r1 - pointer to registers on stack
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@
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mov r0, r2 @ pass address of aborted instruction
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mov r1, #5
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mov.a asr, r17
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mov r2, sp @ regs
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b.l do_PrefetchAbort @ call abort handler
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@
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@ INTRs off again before pulling preserved data off the stack
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@
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disable_irq r0
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@
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@ restore BSR and restart the instruction
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@
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ldw r2, [sp+], #S_PSR
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priv_exit r2 @ return from exception
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ENDPROC(__pabt_priv)
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.align 5
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.LCcralign:
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.word cr_alignment
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.align 5
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__dabt_user:
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user_entry
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#ifdef CONFIG_UNICORE_FPU_F64
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cff ip, s31
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cand.a ip, #0x08000000 @ FPU execption traps?
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beq 209f
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ldw ip, [sp+], #S_PC
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add ip, ip, #4
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stw ip, [sp+], #S_PC
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@
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@ fall through to the emulation code, which returns using r19 if
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@ it has emulated the instruction, or the more conventional lr
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@ if we are to treat this as a real extended instruction
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@
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@ r0 - instruction
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@
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1: ldw.u r0, [r2]
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adr r19, ret_from_exception
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adr lr, 209f
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@
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@ fallthrough to call do_uc_f64
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@
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/*
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* Check whether the instruction is a co-processor instruction.
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* If yes, we need to call the relevant co-processor handler.
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*
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* Note that we don't do a full check here for the co-processor
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* instructions; all instructions with bit 27 set are well
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* defined. The only instructions that should fault are the
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* co-processor instructions.
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*
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* Emulators may wish to make use of the following registers:
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* r0 = instruction opcode.
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* r2 = PC
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* r19 = normal "successful" return address
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* r20 = this threads thread_info structure.
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* lr = unrecognised instruction return address
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*/
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get_thread_info r20 @ get current thread
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and r8, r0, #0x00003c00 @ mask out CP number
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mov r7, #1
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stb r7, [r20+], #TI_USED_CP + 2 @ set appropriate used_cp[]
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@ F64 hardware support entry point.
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@ r0 = faulted instruction
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@ r19 = return address
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@ r20 = fp_state
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enable_irq r4
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add r20, r20, #TI_FPSTATE @ r20 = workspace
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cff r1, s31 @ get fpu FPSCR
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andn r2, r1, #0x08000000
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ctf r2, s31 @ clear 27 bit
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mov r2, sp @ nothing stacked - regdump is at TOS
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mov lr, r19 @ setup for a return to the user code
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@ Now call the C code to package up the bounce to the support code
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@ r0 holds the trigger instruction
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@ r1 holds the FPSCR value
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@ r2 pointer to register dump
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b ucf64_exchandler
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209:
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#endif
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@
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@ Call the processor-specific abort handler:
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@
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@ r2 - aborted context pc
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@ r3 - aborted context asr
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@
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@ The abort handler must return the aborted address in r0, and
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@ the fault status register in r1.
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@
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movc r1, p0.c3, #0 @ get FSR
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movc r0, p0.c4, #0 @ get FAR
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@
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@ INTRs on, then call the main handler
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@
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enable_irq r2
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mov r2, sp
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adr lr, ret_from_exception
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b do_DataAbort
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ENDPROC(__dabt_user)
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.align 5
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__intr_user:
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user_entry
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get_thread_info tsk
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intr_handler
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mov why, #0
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b ret_to_user
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ENDPROC(__intr_user)
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.ltorg
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.align 5
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__extn_user:
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user_entry
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mov r0, sp
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mov r1, asr
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b bad_mode
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ENDPROC(__extn_user)
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.align 5
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__pabt_user:
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user_entry
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mov r0, r2 @ pass address of aborted instruction.
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mov r1, #5
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enable_irq r1 @ Enable interrupts
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mov r2, sp @ regs
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b.l do_PrefetchAbort @ call abort handler
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/* fall through */
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/*
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* This is the return code to user mode for abort handlers
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*/
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ENTRY(ret_from_exception)
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get_thread_info tsk
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mov why, #0
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b ret_to_user
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ENDPROC(__pabt_user)
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ENDPROC(ret_from_exception)
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/*
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* Register switch for UniCore V2 processors
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* r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
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* previous and next are guaranteed not to be the same.
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*/
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ENTRY(__switch_to)
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add ip, r1, #TI_CPU_SAVE
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stm.w (r4 - r15), [ip]+
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stm.w (r16 - r27, sp, lr), [ip]+
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#ifdef CONFIG_UNICORE_FPU_F64
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add ip, r1, #TI_FPSTATE
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sfm.w (f0 - f7 ), [ip]+
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sfm.w (f8 - f15), [ip]+
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sfm.w (f16 - f23), [ip]+
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sfm.w (f24 - f31), [ip]+
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cff r4, s31
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stw r4, [ip]
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add ip, r2, #TI_FPSTATE
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lfm.w (f0 - f7 ), [ip]+
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lfm.w (f8 - f15), [ip]+
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lfm.w (f16 - f23), [ip]+
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lfm.w (f24 - f31), [ip]+
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ldw r4, [ip]
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ctf r4, s31
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#endif
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add ip, r2, #TI_CPU_SAVE
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ldm.w (r4 - r15), [ip]+
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ldm (r16 - r27, sp, pc), [ip]+ @ Load all regs saved previously
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ENDPROC(__switch_to)
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.align 5
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/*
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* This is the fast syscall return path. We do as little as
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* possible here, and this includes saving r0 back into the PRIV
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* stack.
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*/
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ret_fast_syscall:
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disable_irq r1 @ disable interrupts
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ldw r1, [tsk+], #TI_FLAGS
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cand.a r1, #_TIF_WORK_MASK
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bne fast_work_pending
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@ fast_restore_user_regs
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restore_user_regs fast = 1, offset = S_OFF
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/*
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* Ok, we need to do extra processing, enter the slow path.
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*/
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fast_work_pending:
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stw.w r0, [sp+], #S_R0+S_OFF @ returned r0
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work_pending:
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cand.a r1, #_TIF_NEED_RESCHED
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bne work_resched
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mov r0, sp @ 'regs'
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mov r2, why @ 'syscall'
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cand.a r1, #_TIF_SIGPENDING @ delivering a signal?
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cmovne why, #0 @ prevent further restarts
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b.l do_notify_resume
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b ret_slow_syscall @ Check work again
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work_resched:
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b.l schedule
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/*
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* "slow" syscall return path. "why" tells us if this was a real syscall.
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*/
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ENTRY(ret_to_user)
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ret_slow_syscall:
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disable_irq r1 @ disable interrupts
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get_thread_info tsk @ epip4d, one path error?!
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ldw r1, [tsk+], #TI_FLAGS
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cand.a r1, #_TIF_WORK_MASK
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bne work_pending
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no_work_pending:
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@ slow_restore_user_regs
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restore_user_regs fast = 0, offset = 0
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ENDPROC(ret_to_user)
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/*
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* This is how we return from a fork.
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*/
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ENTRY(ret_from_fork)
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b.l schedule_tail
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b ret_slow_syscall
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ENDPROC(ret_from_fork)
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ENTRY(ret_from_kernel_thread)
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b.l schedule_tail
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mov r0, r5
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adr lr, ret_slow_syscall
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mov pc, r4
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ENDPROC(ret_from_kernel_thread)
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/*=============================================================================
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* SWI handler
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*-----------------------------------------------------------------------------
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*/
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.align 5
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ENTRY(vector_swi)
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sub sp, sp, #S_FRAME_SIZE
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stm (r0 - r15), [sp]+ @ Calling r0 - r15
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add r8, sp, #S_R16
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stm (r16 - r28), [r8]+ @ Calling r16 - r28
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add r8, sp, #S_PC
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stur (sp, lr), [r8-] @ Calling sp, lr
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mov r8, bsr @ called from non-REAL mode
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stw lr, [sp+], #S_PC @ Save calling PC
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stw r8, [sp+], #S_PSR @ Save ASR
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stw r0, [sp+], #S_OLD_R0 @ Save OLD_R0
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zero_fp
|
|
/*
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* Get the system call number.
|
*/
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sub ip, lr, #4
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ldw.u scno, [ip] @ get SWI instruction
|
|
#ifdef CONFIG_ALIGNMENT_TRAP
|
ldw ip, __cr_alignment
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ldw ip, [ip]
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movc p0.c1, ip, #0 @ update control register
|
#endif
|
enable_irq ip
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|
get_thread_info tsk
|
ldw tbl, =sys_call_table @ load syscall table pointer
|
|
andn scno, scno, #0xff000000 @ mask off SWI op-code
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andn scno, scno, #0x00ff0000 @ mask off SWI op-code
|
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stm.w (r4, r5), [sp-] @ push fifth and sixth args
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ldw ip, [tsk+], #TI_FLAGS @ check for syscall tracing
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cand.a ip, #_TIF_SYSCALL_TRACE @ are we tracing syscalls?
|
bne __sys_trace
|
|
csub.a scno, #__NR_syscalls @ check upper syscall limit
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adr lr, ret_fast_syscall @ return address
|
bea 1f
|
ldw pc, [tbl+], scno << #2 @ call sys_* routine
|
1:
|
add r1, sp, #S_OFF
|
2: mov why, #0 @ no longer a real syscall
|
b sys_ni_syscall @ not private func
|
|
/*
|
* This is the really slow path. We're going to be doing
|
* context switches, and waiting for our parent to respond.
|
*/
|
__sys_trace:
|
mov r2, scno
|
add r1, sp, #S_OFF
|
mov r0, #0 @ trace entry [IP = 0]
|
b.l syscall_trace
|
|
adr lr, __sys_trace_return @ return address
|
mov scno, r0 @ syscall number (possibly new)
|
add r1, sp, #S_R0 + S_OFF @ pointer to regs
|
csub.a scno, #__NR_syscalls @ check upper syscall limit
|
bea 2b
|
ldm (r0 - r3), [r1]+ @ have to reload r0 - r3
|
ldw pc, [tbl+], scno << #2 @ call sys_* routine
|
|
__sys_trace_return:
|
stw.w r0, [sp+], #S_R0 + S_OFF @ save returned r0
|
mov r2, scno
|
mov r1, sp
|
mov r0, #1 @ trace exit [IP = 1]
|
b.l syscall_trace
|
b ret_slow_syscall
|
|
.align 5
|
#ifdef CONFIG_ALIGNMENT_TRAP
|
.type __cr_alignment, #object
|
__cr_alignment:
|
.word cr_alignment
|
#endif
|
.ltorg
|
|
ENTRY(sys_rt_sigreturn)
|
add r0, sp, #S_OFF
|
mov why, #0 @ prevent syscall restart handling
|
b __sys_rt_sigreturn
|
ENDPROC(sys_rt_sigreturn)
|
|
__INIT
|
|
/*
|
* Vector stubs.
|
*
|
* This code is copied to 0xffff0200 so we can use branches in the
|
* vectors, rather than ldr's. Note that this code must not
|
* exceed 0x300 bytes.
|
*
|
* Common stub entry macro:
|
* Enter in INTR mode, bsr = PRIV/USER ASR, lr = PRIV/USER PC
|
*
|
* SP points to a minimal amount of processor-private memory, the address
|
* of which is copied into r0 for the mode specific abort handler.
|
*/
|
.macro vector_stub, name, mode
|
.align 5
|
|
vector_\name:
|
@
|
@ Save r0, lr_<exception> (parent PC) and bsr_<exception>
|
@ (parent ASR)
|
@
|
stw r0, [sp]
|
stw lr, [sp+], #4 @ save r0, lr
|
mov lr, bsr
|
stw lr, [sp+], #8 @ save bsr
|
|
@
|
@ Prepare for PRIV mode. INTRs remain disabled.
|
@
|
mov r0, asr
|
xor r0, r0, #(\mode ^ PRIV_MODE)
|
mov.a bsr, r0
|
|
@
|
@ the branch table must immediately follow this code
|
@
|
and lr, lr, #0x03
|
add lr, lr, #1
|
mov r0, sp
|
ldw lr, [pc+], lr << #2
|
mov.a pc, lr @ branch to handler in PRIV mode
|
ENDPROC(vector_\name)
|
.align 2
|
@ handler addresses follow this label
|
.endm
|
|
.globl __stubs_start
|
__stubs_start:
|
/*
|
* Interrupt dispatcher
|
*/
|
vector_stub intr, INTR_MODE
|
|
.long __intr_user @ 0 (USER)
|
.long __invalid @ 1
|
.long __invalid @ 2
|
.long __intr_priv @ 3 (PRIV)
|
|
/*
|
* Data abort dispatcher
|
* Enter in ABT mode, bsr = USER ASR, lr = USER PC
|
*/
|
vector_stub dabt, ABRT_MODE
|
|
.long __dabt_user @ 0 (USER)
|
.long __invalid @ 1
|
.long __invalid @ 2 (INTR)
|
.long __dabt_priv @ 3 (PRIV)
|
|
/*
|
* Prefetch abort dispatcher
|
* Enter in ABT mode, bsr = USER ASR, lr = USER PC
|
*/
|
vector_stub pabt, ABRT_MODE
|
|
.long __pabt_user @ 0 (USER)
|
.long __invalid @ 1
|
.long __invalid @ 2 (INTR)
|
.long __pabt_priv @ 3 (PRIV)
|
|
/*
|
* Undef instr entry dispatcher
|
* Enter in EXTN mode, bsr = PRIV/USER ASR, lr = PRIV/USER PC
|
*/
|
vector_stub extn, EXTN_MODE
|
|
.long __extn_user @ 0 (USER)
|
.long __invalid @ 1
|
.long __invalid @ 2 (INTR)
|
.long __extn_priv @ 3 (PRIV)
|
|
/*
|
* We group all the following data together to optimise
|
* for CPUs with separate I & D caches.
|
*/
|
.align 5
|
|
.LCvswi:
|
.word vector_swi
|
|
.globl __stubs_end
|
__stubs_end:
|
|
.equ stubs_offset, __vectors_start + 0x200 - __stubs_start
|
|
.globl __vectors_start
|
__vectors_start:
|
jepriv SYS_ERROR0
|
b vector_extn + stubs_offset
|
ldw pc, .LCvswi + stubs_offset
|
b vector_pabt + stubs_offset
|
b vector_dabt + stubs_offset
|
jepriv SYS_ERROR0
|
b vector_intr + stubs_offset
|
jepriv SYS_ERROR0
|
|
.globl __vectors_end
|
__vectors_end:
|
|
.data
|
|
.globl cr_alignment
|
.globl cr_no_alignment
|
cr_alignment:
|
.space 4
|
cr_no_alignment:
|
.space 4
|
