/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* PKUnity AHB-PCI Bridge Registers
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*/
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/*
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* AHB/PCI fixed physical address for pci addess configuration
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*/
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/*
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* PCICFG Bridge Base Reg.
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*/
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#define PCICFG_BRIBASE (PKUNITY_PCICFG_BASE + 0x0000)
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/*
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* PCICFG Address Reg.
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*/
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#define PCICFG_ADDR (PKUNITY_PCICFG_BASE + 0x0004)
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/*
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* PCICFG Address Reg.
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*/
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#define PCICFG_DATA (PKUNITY_PCICFG_BASE + 0x0008)
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/*
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* PCI Bridge configuration space
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*/
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#define PCIBRI_ID (PKUNITY_PCIBRI_BASE + 0x0000)
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#define PCIBRI_CMD (PKUNITY_PCIBRI_BASE + 0x0004)
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#define PCIBRI_CLASS (PKUNITY_PCIBRI_BASE + 0x0008)
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#define PCIBRI_LTR (PKUNITY_PCIBRI_BASE + 0x000C)
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#define PCIBRI_BAR0 (PKUNITY_PCIBRI_BASE + 0x0010)
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#define PCIBRI_BAR1 (PKUNITY_PCIBRI_BASE + 0x0014)
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#define PCIBRI_BAR2 (PKUNITY_PCIBRI_BASE + 0x0018)
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#define PCIBRI_BAR3 (PKUNITY_PCIBRI_BASE + 0x001C)
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#define PCIBRI_BAR4 (PKUNITY_PCIBRI_BASE + 0x0020)
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#define PCIBRI_BAR5 (PKUNITY_PCIBRI_BASE + 0x0024)
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#define PCIBRI_PCICTL0 (PKUNITY_PCIBRI_BASE + 0x0100)
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#define PCIBRI_PCIBAR0 (PKUNITY_PCIBRI_BASE + 0x0104)
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#define PCIBRI_PCIAMR0 (PKUNITY_PCIBRI_BASE + 0x0108)
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#define PCIBRI_PCITAR0 (PKUNITY_PCIBRI_BASE + 0x010C)
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#define PCIBRI_PCICTL1 (PKUNITY_PCIBRI_BASE + 0x0110)
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#define PCIBRI_PCIBAR1 (PKUNITY_PCIBRI_BASE + 0x0114)
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#define PCIBRI_PCIAMR1 (PKUNITY_PCIBRI_BASE + 0x0118)
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#define PCIBRI_PCITAR1 (PKUNITY_PCIBRI_BASE + 0x011C)
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#define PCIBRI_PCICTL2 (PKUNITY_PCIBRI_BASE + 0x0120)
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#define PCIBRI_PCIBAR2 (PKUNITY_PCIBRI_BASE + 0x0124)
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#define PCIBRI_PCIAMR2 (PKUNITY_PCIBRI_BASE + 0x0128)
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#define PCIBRI_PCITAR2 (PKUNITY_PCIBRI_BASE + 0x012C)
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#define PCIBRI_PCICTL3 (PKUNITY_PCIBRI_BASE + 0x0130)
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#define PCIBRI_PCIBAR3 (PKUNITY_PCIBRI_BASE + 0x0134)
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#define PCIBRI_PCIAMR3 (PKUNITY_PCIBRI_BASE + 0x0138)
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#define PCIBRI_PCITAR3 (PKUNITY_PCIBRI_BASE + 0x013C)
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#define PCIBRI_PCICTL4 (PKUNITY_PCIBRI_BASE + 0x0140)
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#define PCIBRI_PCIBAR4 (PKUNITY_PCIBRI_BASE + 0x0144)
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#define PCIBRI_PCIAMR4 (PKUNITY_PCIBRI_BASE + 0x0148)
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#define PCIBRI_PCITAR4 (PKUNITY_PCIBRI_BASE + 0x014C)
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#define PCIBRI_PCICTL5 (PKUNITY_PCIBRI_BASE + 0x0150)
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#define PCIBRI_PCIBAR5 (PKUNITY_PCIBRI_BASE + 0x0154)
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#define PCIBRI_PCIAMR5 (PKUNITY_PCIBRI_BASE + 0x0158)
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#define PCIBRI_PCITAR5 (PKUNITY_PCIBRI_BASE + 0x015C)
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#define PCIBRI_AHBCTL0 (PKUNITY_PCIBRI_BASE + 0x0180)
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#define PCIBRI_AHBBAR0 (PKUNITY_PCIBRI_BASE + 0x0184)
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#define PCIBRI_AHBAMR0 (PKUNITY_PCIBRI_BASE + 0x0188)
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#define PCIBRI_AHBTAR0 (PKUNITY_PCIBRI_BASE + 0x018C)
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#define PCIBRI_AHBCTL1 (PKUNITY_PCIBRI_BASE + 0x0190)
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#define PCIBRI_AHBBAR1 (PKUNITY_PCIBRI_BASE + 0x0194)
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#define PCIBRI_AHBAMR1 (PKUNITY_PCIBRI_BASE + 0x0198)
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#define PCIBRI_AHBTAR1 (PKUNITY_PCIBRI_BASE + 0x019C)
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#define PCIBRI_AHBCTL2 (PKUNITY_PCIBRI_BASE + 0x01A0)
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#define PCIBRI_AHBBAR2 (PKUNITY_PCIBRI_BASE + 0x01A4)
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#define PCIBRI_AHBAMR2 (PKUNITY_PCIBRI_BASE + 0x01A8)
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#define PCIBRI_AHBTAR2 (PKUNITY_PCIBRI_BASE + 0x01AC)
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#define PCIBRI_AHBCTL3 (PKUNITY_PCIBRI_BASE + 0x01B0)
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#define PCIBRI_AHBBAR3 (PKUNITY_PCIBRI_BASE + 0x01B4)
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#define PCIBRI_AHBAMR3 (PKUNITY_PCIBRI_BASE + 0x01B8)
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#define PCIBRI_AHBTAR3 (PKUNITY_PCIBRI_BASE + 0x01BC)
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#define PCIBRI_AHBCTL4 (PKUNITY_PCIBRI_BASE + 0x01C0)
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#define PCIBRI_AHBBAR4 (PKUNITY_PCIBRI_BASE + 0x01C4)
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#define PCIBRI_AHBAMR4 (PKUNITY_PCIBRI_BASE + 0x01C8)
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#define PCIBRI_AHBTAR4 (PKUNITY_PCIBRI_BASE + 0x01CC)
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#define PCIBRI_AHBCTL5 (PKUNITY_PCIBRI_BASE + 0x01D0)
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#define PCIBRI_AHBBAR5 (PKUNITY_PCIBRI_BASE + 0x01D4)
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#define PCIBRI_AHBAMR5 (PKUNITY_PCIBRI_BASE + 0x01D8)
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#define PCIBRI_AHBTAR5 (PKUNITY_PCIBRI_BASE + 0x01DC)
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#define PCIBRI_CTLx_AT FIELD(1, 1, 2)
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#define PCIBRI_CTLx_PREF FIELD(1, 1, 1)
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#define PCIBRI_CTLx_MRL FIELD(1, 1, 0)
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#define PCIBRI_BARx_ADDR FIELD(0xFFFFFFFC, 30, 2)
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#define PCIBRI_BARx_IO FIELD(1, 1, 0)
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#define PCIBRI_BARx_MEM FIELD(0, 1, 0)
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#define PCIBRI_CMD_IO FIELD(1, 1, 0)
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#define PCIBRI_CMD_MEM FIELD(1, 1, 1)
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