/*
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* Co-processor register definitions for PKUnity SoC and UniCore ISA
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*
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* Copyright (C) 2001-2012 GUAN Xue-tao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __UNICORE_HWDEF_COPRO_H__
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#define __UNICORE_HWDEF_COPRO_H__
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/*
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* Control Register bits (CP#0 CR1)
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*/
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#define CR_M (1 << 0) /* MMU enable */
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#define CR_A (1 << 1) /* Alignment abort enable */
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#define CR_D (1 << 2) /* Dcache enable */
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#define CR_I (1 << 3) /* Icache enable */
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#define CR_B (1 << 4) /* Dcache write mechanism: write back */
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#define CR_T (1 << 5) /* Burst enable */
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#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
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#ifndef __ASSEMBLY__
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#define vectors_high() (cr_alignment & CR_V)
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extern unsigned long cr_no_alignment; /* defined in entry.S */
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extern unsigned long cr_alignment; /* defined in entry.S */
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static inline unsigned int get_cr(void)
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{
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unsigned int val;
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asm("movc %0, p0.c1, #0" : "=r" (val) : : "cc");
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return val;
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}
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static inline void set_cr(unsigned int val)
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{
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asm volatile("movc p0.c1, %0, #0" : : "r" (val) : "cc");
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isb();
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}
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extern void adjust_cr(unsigned long mask, unsigned long set);
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#endif /* __ASSEMBLY__ */
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#endif /* __UNICORE_HWDEF_COPRO_H__ */
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