/*
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* Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
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* Author: Chris Zhong<zyw@rock-chips.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/regmap.h>
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#include "pm.h"
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#include "embedded/rk3288_ddr.h"
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#include "embedded/rk3288_resume.h"
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void __iomem *rk3288_regulator_pwm_addr;
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void __iomem *rk3288_ddr_ctrl_addr[RK3288_NUM_DDR_PORTS];
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void __iomem *rk3288_phy_addr[RK3288_NUM_DDR_PORTS];
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void __iomem *rk3288_msch_addr[RK3288_NUM_DDR_PORTS];
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static const char * const rk3288_ddr_clk_names[] = {
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"pclk_ddrupctl0",
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"pclk_publ0",
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"pclk_ddrupctl1",
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"pclk_publ1",
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"aclk_dmac1",
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};
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#define NUM_DDR_CLK_NAMES ARRAY_SIZE(rk3288_ddr_clk_names)
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static struct clk *rk3288_ddr_clks[NUM_DDR_CLK_NAMES];
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static const u32 rk3288_pwm_reg[] = {
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0x4, /* PERIOD */
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0x8, /* DUTY */
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0xc, /* CTRL */
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};
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#define NUM_PWM_REGS ARRAY_SIZE(rk3288_pwm_reg)
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static const u32 rk3288_ddr_phy_dll_reg[] = {
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DDR_PUBL_DLLGCR,
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DDR_PUBL_ACDLLCR,
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DDR_PUBL_DX0DLLCR,
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DDR_PUBL_DX1DLLCR,
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DDR_PUBL_DX2DLLCR,
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DDR_PUBL_DX3DLLCR,
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DDR_PUBL_PIR,
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};
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#define NUM_DDR_PHY_DLL_REGS ARRAY_SIZE(rk3288_ddr_phy_dll_reg)
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static const u32 rk3288_ddr_ctrl_reg[] = {
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DDR_PCTL_TOGCNT1U,
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DDR_PCTL_TINIT,
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DDR_PCTL_TEXSR,
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DDR_PCTL_TINIT,
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DDR_PCTL_TRSTH,
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DDR_PCTL_TOGCNT100N,
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DDR_PCTL_TREFI,
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DDR_PCTL_TMRD,
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DDR_PCTL_TRFC,
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DDR_PCTL_TRP,
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DDR_PCTL_TRTW,
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DDR_PCTL_TAL,
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DDR_PCTL_TCL,
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DDR_PCTL_TCWL,
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DDR_PCTL_TRAS,
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DDR_PCTL_TRC,
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DDR_PCTL_TRCD,
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DDR_PCTL_TRRD,
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DDR_PCTL_TRTP,
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DDR_PCTL_TWR,
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DDR_PCTL_TWTR,
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DDR_PCTL_TEXSR,
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DDR_PCTL_TXP,
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DDR_PCTL_TXPDLL,
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DDR_PCTL_TZQCS,
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DDR_PCTL_TZQCSI,
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DDR_PCTL_TDQS,
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DDR_PCTL_TCKSRE,
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DDR_PCTL_TCKSRX,
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DDR_PCTL_TCKE,
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DDR_PCTL_TMOD,
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DDR_PCTL_TRSTL,
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DDR_PCTL_TZQCL,
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DDR_PCTL_TMRR,
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DDR_PCTL_TCKESR,
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DDR_PCTL_TDPD,
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DDR_PCTL_SCFG,
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DDR_PCTL_CMDTSTATEN,
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DDR_PCTL_MCFG1,
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DDR_PCTL_MCFG,
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DDR_PCTL_DFITCTRLDELAY,
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DDR_PCTL_DFIODTCFG,
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DDR_PCTL_DFIODTCFG1,
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DDR_PCTL_DFIODTRANKMAP,
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DDR_PCTL_DFITPHYWRDATA,
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DDR_PCTL_DFITPHYWRLAT,
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DDR_PCTL_DFITRDDATAEN,
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DDR_PCTL_DFITPHYRDLAT,
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DDR_PCTL_DFITPHYUPDTYPE0,
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DDR_PCTL_DFITPHYUPDTYPE1,
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DDR_PCTL_DFITPHYUPDTYPE2,
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DDR_PCTL_DFITPHYUPDTYPE3,
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DDR_PCTL_DFITCTRLUPDMIN,
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DDR_PCTL_DFITCTRLUPDMAX,
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DDR_PCTL_DFITCTRLUPDDLY,
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DDR_PCTL_DFIUPDCFG,
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DDR_PCTL_DFITREFMSKI,
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DDR_PCTL_DFITCTRLUPDI,
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DDR_PCTL_DFISTCFG0,
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DDR_PCTL_DFISTCFG1,
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DDR_PCTL_DFITDRAMCLKEN,
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DDR_PCTL_DFITDRAMCLKDIS,
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DDR_PCTL_DFISTCFG2,
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DDR_PCTL_DFILPCFG0,
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};
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#define NUM_DDR_CTRL_REGS ARRAY_SIZE(rk3288_ddr_ctrl_reg)
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static const u32 rk3288_ddr_phy_reg[] = {
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DDR_PUBL_DTPR0,
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DDR_PUBL_DTPR1,
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DDR_PUBL_DTPR2,
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DDR_PUBL_MR0,
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DDR_PUBL_MR1,
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DDR_PUBL_MR2,
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DDR_PUBL_MR3,
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DDR_PUBL_PGCR,
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DDR_PUBL_PTR0,
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DDR_PUBL_PTR1,
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DDR_PUBL_PTR2,
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DDR_PUBL_ACIOCR,
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DDR_PUBL_DXCCR,
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DDR_PUBL_DSGCR,
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DDR_PUBL_DCR,
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DDR_PUBL_ODTCR,
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DDR_PUBL_DTAR,
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DDR_PUBL_DX0GCR,
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DDR_PUBL_DX1GCR,
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DDR_PUBL_DX2GCR,
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DDR_PUBL_DX3GCR,
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DDR_PUBL_DX0DQTR,
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DDR_PUBL_DX0DQSTR,
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DDR_PUBL_DX1DQTR,
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DDR_PUBL_DX1DQSTR,
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DDR_PUBL_DX2DQTR,
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DDR_PUBL_DX2DQSTR,
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DDR_PUBL_DX3DQTR,
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DDR_PUBL_DX3DQSTR,
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};
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#define NUM_DDR_PHY_REGS ARRAY_SIZE(rk3288_ddr_phy_reg)
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static const u32 rk3288_ddr_msch_reg[] = {
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DDR_MSCH_DDRCONF,
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DDR_MSCH_DDRTIMING,
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DDR_MSCH_DDRMODE,
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DDR_MSCH_READLATENCY,
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DDR_MSCH_ACTIVATE,
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DDR_MSCH_DEVTODEV,
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};
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#define NUM_DDR_MSCH_REGS ARRAY_SIZE(rk3288_ddr_msch_reg)
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static const u32 rk3288_ddr_phy_zqcr_reg[] = {
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DDR_PUBL_ZQ0CR0,
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DDR_PUBL_ZQ1CR0,
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};
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#define NUM_DDR_PHY_ZQCR_REGS ARRAY_SIZE(rk3288_ddr_phy_zqcr_reg)
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static void rk3288_ddr_reg_save(void __iomem *regbase, const u32 reg_list[],
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int num_reg, u32 *vals)
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{
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int i;
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for (i = 0; i < num_reg; i++)
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vals[i] = readl_relaxed(regbase + reg_list[i]);
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}
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static void rk3288_ddr_save_offsets(u32 *dst_offsets, const u32 *src_offsets,
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int num_offsets, int max_offsets)
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{
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memcpy(dst_offsets, src_offsets, sizeof(*dst_offsets) * num_offsets);
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/*
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* Bytes are precious in the restore code, so we don't actually store
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* a count. We just put a 0xffffffff if num >= max.
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*/
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if (num_offsets < max_offsets)
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dst_offsets[num_offsets] = RK3288_BOGUS_OFFSET;
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}
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int rk3288_ddr_suspend(struct rk3288_ddr_save_data *ddr_save)
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{
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int ret;
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int i;
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for (i = 0; i < ARRAY_SIZE(rk3288_ddr_clk_names); i++) {
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ret = clk_enable(rk3288_ddr_clks[i]);
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if (ret) {
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pr_err("%s: Couldn't enable clock %s\n", __func__,
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rk3288_ddr_clk_names[i]);
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goto err;
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}
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}
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if (rk3288_regulator_pwm_addr)
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rk3288_ddr_reg_save(rk3288_regulator_pwm_addr, rk3288_pwm_reg,
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NUM_PWM_REGS, ddr_save->pwm_vals);
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rk3288_ddr_reg_save(rk3288_ddr_ctrl_addr[0], rk3288_ddr_ctrl_reg,
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NUM_DDR_CTRL_REGS, ddr_save->ctrl_vals);
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/* TODO: need to support only one channel of DDR? */
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for (i = 0; i < RK3288_NUM_DDR_PORTS; i++) {
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rk3288_ddr_reg_save(rk3288_phy_addr[i], rk3288_ddr_phy_reg,
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NUM_DDR_PHY_REGS, ddr_save->phy_vals[i]);
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rk3288_ddr_reg_save(rk3288_phy_addr[i], rk3288_ddr_phy_dll_reg,
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NUM_DDR_PHY_DLL_REGS,
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ddr_save->phy_dll_vals[i]);
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rk3288_ddr_reg_save(rk3288_msch_addr[i], rk3288_ddr_msch_reg,
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NUM_DDR_MSCH_REGS, ddr_save->msch_vals[i]);
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}
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rk3288_ddr_reg_save(rk3288_phy_addr[0], rk3288_ddr_phy_zqcr_reg,
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NUM_DDR_PHY_ZQCR_REGS, ddr_save->phy_zqcr_vals);
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return 0;
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err:
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for (; i > 0; i--)
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clk_disable(rk3288_ddr_clks[i - 1]);
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return ret;
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}
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void rk3288_ddr_resume(void)
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{
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int i;
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for (i = NUM_DDR_CLK_NAMES; i > 0; i--)
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clk_disable(rk3288_ddr_clks[i - 1]);
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}
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/**
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* rk3288_get_regulator_pwm_np - Get the PWM regulator node, if present
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*
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* It's common (but not required) that an rk3288 board uses one of the
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* PWMs on the rk3288 as a regulator. We'll see if we're in that case. If we
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* are we'll return a "np" for the PWM to save. If not, we'll return NULL.
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* If we have an unexpected error we'll return an ERR_PTR.
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*
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* NOTE: this whole concept of needing to restore the voltage immediately after
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* resume only makes sense for the PWMs built into rk3288. Any external
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* regulators or external PWMs ought to keep their state.
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*/
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static struct device_node * __init rk3288_get_regulator_pwm_np(
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struct device_node *dmc_np)
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{
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struct device_node *np;
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struct of_phandle_args args;
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int ret;
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/* Look for the supply to the memory controller; OK if not there */
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np = of_parse_phandle(dmc_np, "logic-supply", 0);
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if (!np)
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return NULL;
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/* Check to see if it's a PWM regulator; OK if it's not */
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if (!of_device_is_compatible(np, "pwm-regulator")) {
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of_node_put(np);
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return NULL;
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}
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/* If it's a PWM regulator, we'd better be able to get the PWM */
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ret = of_parse_phandle_with_args(np, "pwms", "#pwm-cells", 0, &args);
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of_node_put(np);
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if (ret) {
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pr_err("%s(): can't parse \"pwms\" property\n", __func__);
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return ERR_PTR(ret);
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}
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/*
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* It seems highly unlikely that we'd have a PWM supplying a PWM
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* regulator on an rk3288 that isn't a rk3288 PWM. In such a case
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* it's unlikely that the PWM will lose its state. We'll throw up a
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* warning just because this is so strange, but we won't treat it as
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* an error.
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*/
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if (!of_device_is_compatible(args.np, "rockchip,rk3288-pwm")) {
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pr_warn("%s(): unexpected PWM for regulator\n", __func__);
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of_node_put(args.np);
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return NULL;
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}
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return args.np;
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}
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int __init rk3288_ddr_suspend_init(struct rk3288_ddr_save_data *ddr_save)
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{
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struct device_node *dmc_np = NULL, *noc_np = NULL, *pwm_np = NULL;
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int ret;
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int i;
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dmc_np = of_find_compatible_node(NULL, NULL, "rockchip,rk3288-dmc");
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if (!dmc_np) {
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pr_err("%s: could not find dmc dt node\n", __func__);
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ret = -ENODEV;
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goto err;
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}
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noc_np = of_find_compatible_node(NULL, NULL, "rockchip,rk3288-noc");
|
if (!noc_np) {
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pr_err("%s: could not find noc node\n", __func__);
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ret = -ENODEV;
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goto err;
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}
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|
pwm_np = rk3288_get_regulator_pwm_np(dmc_np);
|
if (IS_ERR(pwm_np)) {
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ret = PTR_ERR(pwm_np);
|
goto err;
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}
|
|
/* Do the offsets and saving of the PWM together */
|
if (pwm_np) {
|
struct resource res;
|
|
rk3288_regulator_pwm_addr = of_iomap(pwm_np, 0);
|
if (!rk3288_regulator_pwm_addr) {
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pr_err("%s: could not map PWM\n", __func__);
|
ret = -ENOMEM;
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goto err;
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}
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|
ret = of_address_to_resource(pwm_np, 0, &res);
|
if (ret) {
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pr_err("%s: could not get PWM phy addr\n", __func__);
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goto err;
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}
|
|
BUILD_BUG_ON(NUM_PWM_REGS > RK3288_MAX_PWM_REGS);
|
rk3288_ddr_save_offsets(ddr_save->pwm_addrs,
|
rk3288_pwm_reg,
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NUM_PWM_REGS,
|
RK3288_MAX_PWM_REGS);
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/* Adjust to store full address, since there are many PWMs */
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for (i = 0; i < NUM_PWM_REGS; i++)
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ddr_save->pwm_addrs[i] += res.start;
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}
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/* Copy offsets in */
|
BUILD_BUG_ON(NUM_DDR_PHY_DLL_REGS > RK3288_MAX_DDR_PHY_DLL_REGS);
|
rk3288_ddr_save_offsets(ddr_save->phy_dll_offsets,
|
rk3288_ddr_phy_dll_reg,
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NUM_DDR_PHY_DLL_REGS,
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RK3288_MAX_DDR_PHY_DLL_REGS);
|
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BUILD_BUG_ON(NUM_DDR_CTRL_REGS > RK3288_MAX_DDR_CTRL_REGS);
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rk3288_ddr_save_offsets(ddr_save->ctrl_offsets,
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rk3288_ddr_ctrl_reg,
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NUM_DDR_CTRL_REGS,
|
RK3288_MAX_DDR_CTRL_REGS);
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BUILD_BUG_ON(NUM_DDR_PHY_REGS > RK3288_MAX_DDR_PHY_REGS);
|
rk3288_ddr_save_offsets(ddr_save->phy_offsets,
|
rk3288_ddr_phy_reg,
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NUM_DDR_PHY_REGS,
|
RK3288_MAX_DDR_PHY_REGS);
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|
BUILD_BUG_ON(ARRAY_SIZE(rk3288_ddr_msch_reg) >
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RK3288_MAX_DDR_MSCH_REGS);
|
rk3288_ddr_save_offsets(ddr_save->msch_offsets,
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rk3288_ddr_msch_reg,
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NUM_DDR_MSCH_REGS,
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RK3288_MAX_DDR_MSCH_REGS);
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BUILD_BUG_ON(NUM_DDR_PHY_ZQCR_REGS > RK3288_MAX_DDR_PHY_ZQCR_REGS);
|
rk3288_ddr_save_offsets(ddr_save->phy_zqcr_offsets,
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rk3288_ddr_phy_zqcr_reg,
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NUM_DDR_PHY_ZQCR_REGS,
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RK3288_MAX_DDR_PHY_ZQCR_REGS);
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for (i = 0; i < RK3288_NUM_DDR_PORTS; i++) {
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rk3288_ddr_ctrl_addr[i] = of_iomap(dmc_np, i * 2);
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if (!rk3288_ddr_ctrl_addr[i]) {
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pr_err("%s: could not map ddr ctrl\n", __func__);
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ret = -ENOMEM;
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goto err;
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}
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rk3288_phy_addr[i] = of_iomap(dmc_np, i * 2 + 1);
|
if (!rk3288_phy_addr[i]) {
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pr_err("%s: could not map phy\n", __func__);
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ret = -ENOMEM;
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goto err;
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}
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}
|
|
for (i = 0; i < NUM_DDR_CLK_NAMES; i++) {
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rk3288_ddr_clks[i] =
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of_clk_get_by_name(dmc_np, rk3288_ddr_clk_names[i]);
|
|
if (IS_ERR(rk3288_ddr_clks[i])) {
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pr_err("%s: couldn't get clock %s\n", __func__,
|
rk3288_ddr_clk_names[i]);
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ret = PTR_ERR(rk3288_ddr_clks[i]);
|
goto err;
|
}
|
|
ret = clk_prepare(rk3288_ddr_clks[i]);
|
if (ret) {
|
pr_err("%s: couldn't prepare clock %s\n", __func__,
|
rk3288_ddr_clk_names[i]);
|
clk_put(rk3288_ddr_clks[i]);
|
rk3288_ddr_clks[i] = NULL;
|
goto err;
|
}
|
}
|
|
rk3288_msch_addr[0] = of_iomap(noc_np, 0);
|
if (!rk3288_msch_addr[0]) {
|
pr_err("%s: could not map msch base\n", __func__);
|
ret = -ENOMEM;
|
goto err;
|
}
|
rk3288_msch_addr[1] = rk3288_msch_addr[0] + 0x80;
|
|
ret = 0;
|
goto exit_of;
|
|
err:
|
if (rk3288_msch_addr[0]) {
|
iounmap(rk3288_msch_addr[0]);
|
rk3288_msch_addr[0] = NULL;
|
}
|
|
for (i = 0; i < NUM_DDR_CLK_NAMES; i++)
|
if (!IS_ERR_OR_NULL(rk3288_ddr_clks[i])) {
|
clk_unprepare(rk3288_ddr_clks[i]);
|
clk_put(rk3288_ddr_clks[i]);
|
rk3288_ddr_clks[i] = NULL;
|
}
|
|
for (i = 0; i < RK3288_NUM_DDR_PORTS; i++) {
|
if (rk3288_phy_addr[i]) {
|
iounmap(rk3288_phy_addr[i]);
|
rk3288_phy_addr[i] = NULL;
|
}
|
if (rk3288_ddr_ctrl_addr[i]) {
|
iounmap(rk3288_ddr_ctrl_addr[i]);
|
rk3288_ddr_ctrl_addr[i] = NULL;
|
}
|
}
|
|
if (rk3288_regulator_pwm_addr) {
|
iounmap(rk3288_regulator_pwm_addr);
|
rk3288_regulator_pwm_addr = NULL;
|
}
|
|
exit_of:
|
if (pwm_np)
|
of_node_put(pwm_np);
|
if (noc_np)
|
of_node_put(noc_np);
|
if (dmc_np)
|
of_node_put(dmc_np);
|
|
return ret;
|
}
|
