/*
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* (C) 2010,2011 Thomas Renninger <trenn@suse.de>, Novell Inc.
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*
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* Licensed under the terms of the GNU GPL License version 2.
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*
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* PCI initialization based on example code from:
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* Andreas Herrmann <andreas.herrmann3@amd.com>
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*/
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#if defined(__i386__) || defined(__x86_64__)
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <time.h>
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#include <string.h>
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#include <pci/pci.h>
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#include "idle_monitor/cpupower-monitor.h"
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#include "helpers/helpers.h"
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#define PCI_NON_PC0_OFFSET 0xb0
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#define PCI_PC1_OFFSET 0xb4
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#define PCI_PC6_OFFSET 0xb8
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#define PCI_MONITOR_ENABLE_REG 0xe0
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#define PCI_NON_PC0_ENABLE_BIT 0
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#define PCI_PC1_ENABLE_BIT 1
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#define PCI_PC6_ENABLE_BIT 2
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#define PCI_NBP1_STAT_OFFSET 0x98
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#define PCI_NBP1_ACTIVE_BIT 2
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#define PCI_NBP1_ENTERED_BIT 1
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#define PCI_NBP1_CAP_OFFSET 0x90
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#define PCI_NBP1_CAPABLE_BIT 31
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#define OVERFLOW_MS 343597 /* 32 bit register filled at 12500 HZ
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(1 tick per 80ns) */
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enum amd_fam14h_states {NON_PC0 = 0, PC1, PC6, NBP1,
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AMD_FAM14H_STATE_NUM};
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static int fam14h_get_count_percent(unsigned int self_id, double *percent,
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unsigned int cpu);
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static int fam14h_nbp1_count(unsigned int id, unsigned long long *count,
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unsigned int cpu);
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static cstate_t amd_fam14h_cstates[AMD_FAM14H_STATE_NUM] = {
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{
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.name = "!PC0",
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.desc = N_("Package in sleep state (PC1 or deeper)"),
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.id = NON_PC0,
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.range = RANGE_PACKAGE,
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.get_count_percent = fam14h_get_count_percent,
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},
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{
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.name = "PC1",
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.desc = N_("Processor Package C1"),
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.id = PC1,
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.range = RANGE_PACKAGE,
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.get_count_percent = fam14h_get_count_percent,
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},
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{
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.name = "PC6",
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.desc = N_("Processor Package C6"),
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.id = PC6,
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.range = RANGE_PACKAGE,
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.get_count_percent = fam14h_get_count_percent,
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},
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{
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.name = "NBP1",
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.desc = N_("North Bridge P1 boolean counter (returns 0 or 1)"),
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.id = NBP1,
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.range = RANGE_PACKAGE,
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.get_count = fam14h_nbp1_count,
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},
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};
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static struct pci_access *pci_acc;
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static struct pci_dev *amd_fam14h_pci_dev;
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static int nbp1_entered;
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static struct timespec start_time;
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static unsigned long long timediff;
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#ifdef DEBUG
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struct timespec dbg_time;
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long dbg_timediff;
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#endif
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static unsigned long long *previous_count[AMD_FAM14H_STATE_NUM];
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static unsigned long long *current_count[AMD_FAM14H_STATE_NUM];
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static int amd_fam14h_get_pci_info(struct cstate *state,
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unsigned int *pci_offset,
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unsigned int *enable_bit,
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unsigned int cpu)
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{
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switch (state->id) {
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case NON_PC0:
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*enable_bit = PCI_NON_PC0_ENABLE_BIT;
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*pci_offset = PCI_NON_PC0_OFFSET;
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break;
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case PC1:
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*enable_bit = PCI_PC1_ENABLE_BIT;
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*pci_offset = PCI_PC1_OFFSET;
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break;
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case PC6:
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*enable_bit = PCI_PC6_ENABLE_BIT;
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*pci_offset = PCI_PC6_OFFSET;
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break;
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case NBP1:
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*enable_bit = PCI_NBP1_ENTERED_BIT;
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*pci_offset = PCI_NBP1_STAT_OFFSET;
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break;
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default:
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return -1;
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};
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return 0;
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}
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static int amd_fam14h_init(cstate_t *state, unsigned int cpu)
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{
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int enable_bit, pci_offset, ret;
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uint32_t val;
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ret = amd_fam14h_get_pci_info(state, &pci_offset, &enable_bit, cpu);
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if (ret)
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return ret;
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/* NBP1 needs extra treating -> write 1 to D18F6x98 bit 1 for init */
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if (state->id == NBP1) {
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val = pci_read_long(amd_fam14h_pci_dev, pci_offset);
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val |= 1 << enable_bit;
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val = pci_write_long(amd_fam14h_pci_dev, pci_offset, val);
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return ret;
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}
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/* Enable monitor */
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val = pci_read_long(amd_fam14h_pci_dev, PCI_MONITOR_ENABLE_REG);
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dprint("Init %s: read at offset: 0x%x val: %u\n", state->name,
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PCI_MONITOR_ENABLE_REG, (unsigned int) val);
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val |= 1 << enable_bit;
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pci_write_long(amd_fam14h_pci_dev, PCI_MONITOR_ENABLE_REG, val);
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dprint("Init %s: offset: 0x%x enable_bit: %d - val: %u (%u)\n",
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state->name, PCI_MONITOR_ENABLE_REG, enable_bit,
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(unsigned int) val, cpu);
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/* Set counter to zero */
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pci_write_long(amd_fam14h_pci_dev, pci_offset, 0);
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previous_count[state->id][cpu] = 0;
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return 0;
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}
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static int amd_fam14h_disable(cstate_t *state, unsigned int cpu)
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{
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int enable_bit, pci_offset, ret;
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uint32_t val;
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ret = amd_fam14h_get_pci_info(state, &pci_offset, &enable_bit, cpu);
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if (ret)
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return ret;
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val = pci_read_long(amd_fam14h_pci_dev, pci_offset);
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dprint("%s: offset: 0x%x %u\n", state->name, pci_offset, val);
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if (state->id == NBP1) {
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/* was the bit whether NBP1 got entered set? */
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nbp1_entered = (val & (1 << PCI_NBP1_ACTIVE_BIT)) |
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(val & (1 << PCI_NBP1_ENTERED_BIT));
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dprint("NBP1 was %sentered - 0x%x - enable_bit: "
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"%d - pci_offset: 0x%x\n",
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nbp1_entered ? "" : "not ",
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val, enable_bit, pci_offset);
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return ret;
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}
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current_count[state->id][cpu] = val;
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dprint("%s: Current - %llu (%u)\n", state->name,
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current_count[state->id][cpu], cpu);
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dprint("%s: Previous - %llu (%u)\n", state->name,
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previous_count[state->id][cpu], cpu);
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val = pci_read_long(amd_fam14h_pci_dev, PCI_MONITOR_ENABLE_REG);
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val &= ~(1 << enable_bit);
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pci_write_long(amd_fam14h_pci_dev, PCI_MONITOR_ENABLE_REG, val);
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return 0;
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}
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static int fam14h_nbp1_count(unsigned int id, unsigned long long *count,
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unsigned int cpu)
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{
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if (id == NBP1) {
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if (nbp1_entered)
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*count = 1;
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else
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*count = 0;
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return 0;
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}
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return -1;
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}
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static int fam14h_get_count_percent(unsigned int id, double *percent,
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unsigned int cpu)
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{
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unsigned long diff;
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if (id >= AMD_FAM14H_STATE_NUM)
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return -1;
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/* residency count in 80ns -> divide through 12.5 to get us residency */
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diff = current_count[id][cpu] - previous_count[id][cpu];
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if (timediff == 0)
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*percent = 0.0;
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else
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*percent = 100.0 * diff / timediff / 12.5;
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dprint("Timediff: %llu - res~: %lu us - percent: %.2f %%\n",
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timediff, diff * 10 / 125, *percent);
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return 0;
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}
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static int amd_fam14h_start(void)
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{
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int num, cpu;
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clock_gettime(CLOCK_REALTIME, &start_time);
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for (num = 0; num < AMD_FAM14H_STATE_NUM; num++) {
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for (cpu = 0; cpu < cpu_count; cpu++)
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amd_fam14h_init(&amd_fam14h_cstates[num], cpu);
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}
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#ifdef DEBUG
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clock_gettime(CLOCK_REALTIME, &dbg_time);
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dbg_timediff = timespec_diff_us(start_time, dbg_time);
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dprint("Enabling counters took: %lu us\n",
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dbg_timediff);
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#endif
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return 0;
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}
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static int amd_fam14h_stop(void)
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{
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int num, cpu;
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struct timespec end_time;
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clock_gettime(CLOCK_REALTIME, &end_time);
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for (num = 0; num < AMD_FAM14H_STATE_NUM; num++) {
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for (cpu = 0; cpu < cpu_count; cpu++)
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amd_fam14h_disable(&amd_fam14h_cstates[num], cpu);
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}
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#ifdef DEBUG
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clock_gettime(CLOCK_REALTIME, &dbg_time);
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dbg_timediff = timespec_diff_us(end_time, dbg_time);
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dprint("Disabling counters took: %lu ns\n", dbg_timediff);
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#endif
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timediff = timespec_diff_us(start_time, end_time);
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if (timediff / 1000 > OVERFLOW_MS)
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print_overflow_err((unsigned int)timediff / 1000000,
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OVERFLOW_MS / 1000);
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return 0;
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}
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static int is_nbp1_capable(void)
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{
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uint32_t val;
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val = pci_read_long(amd_fam14h_pci_dev, PCI_NBP1_CAP_OFFSET);
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return val & (1 << 31);
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}
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struct cpuidle_monitor *amd_fam14h_register(void)
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{
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int num;
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if (cpupower_cpu_info.vendor != X86_VENDOR_AMD)
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return NULL;
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if (cpupower_cpu_info.family == 0x14)
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strncpy(amd_fam14h_monitor.name, "Fam_14h",
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MONITOR_NAME_LEN - 1);
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else if (cpupower_cpu_info.family == 0x12)
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strncpy(amd_fam14h_monitor.name, "Fam_12h",
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MONITOR_NAME_LEN - 1);
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else
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return NULL;
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/* We do not alloc for nbp1 machine wide counter */
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for (num = 0; num < AMD_FAM14H_STATE_NUM - 1; num++) {
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previous_count[num] = calloc(cpu_count,
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sizeof(unsigned long long));
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current_count[num] = calloc(cpu_count,
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sizeof(unsigned long long));
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}
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/* We need PCI device: Slot 18, Func 6, compare with BKDG
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for fam 12h/14h */
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amd_fam14h_pci_dev = pci_slot_func_init(&pci_acc, 0x18, 6);
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if (amd_fam14h_pci_dev == NULL || pci_acc == NULL)
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return NULL;
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if (!is_nbp1_capable())
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amd_fam14h_monitor.hw_states_num = AMD_FAM14H_STATE_NUM - 1;
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amd_fam14h_monitor.name_len = strlen(amd_fam14h_monitor.name);
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return &amd_fam14h_monitor;
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}
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static void amd_fam14h_unregister(void)
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{
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int num;
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for (num = 0; num < AMD_FAM14H_STATE_NUM - 1; num++) {
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free(previous_count[num]);
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free(current_count[num]);
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}
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pci_cleanup(pci_acc);
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}
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struct cpuidle_monitor amd_fam14h_monitor = {
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.name = "",
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.hw_states = amd_fam14h_cstates,
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.hw_states_num = AMD_FAM14H_STATE_NUM,
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.start = amd_fam14h_start,
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.stop = amd_fam14h_stop,
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.do_register = amd_fam14h_register,
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.unregister = amd_fam14h_unregister,
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.needs_root = 1,
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.overflow_s = OVERFLOW_MS / 1000,
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};
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#endif /* #if defined(__i386__) || defined(__x86_64__) */
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