/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2012-2013 Freescale Semiconductor, Inc.
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*/
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#ifndef __FSL_SAI_H
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#define __FSL_SAI_H
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#include <sound/dmaengine_pcm.h>
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#define FSL_SAI_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
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SNDRV_PCM_FMTBIT_S20_3LE |\
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SNDRV_PCM_FMTBIT_S24_LE |\
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SNDRV_PCM_FMTBIT_S32_LE)
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/* SAI Register Map Register */
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#define FSL_SAI_TCSR 0x00 /* SAI Transmit Control */
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#define FSL_SAI_TCR1 0x04 /* SAI Transmit Configuration 1 */
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#define FSL_SAI_TCR2 0x08 /* SAI Transmit Configuration 2 */
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#define FSL_SAI_TCR3 0x0c /* SAI Transmit Configuration 3 */
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#define FSL_SAI_TCR4 0x10 /* SAI Transmit Configuration 4 */
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#define FSL_SAI_TCR5 0x14 /* SAI Transmit Configuration 5 */
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#define FSL_SAI_TDR 0x20 /* SAI Transmit Data */
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#define FSL_SAI_TFR 0x40 /* SAI Transmit FIFO */
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#define FSL_SAI_TMR 0x60 /* SAI Transmit Mask */
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#define FSL_SAI_RCSR 0x80 /* SAI Receive Control */
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#define FSL_SAI_RCR1 0x84 /* SAI Receive Configuration 1 */
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#define FSL_SAI_RCR2 0x88 /* SAI Receive Configuration 2 */
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#define FSL_SAI_RCR3 0x8c /* SAI Receive Configuration 3 */
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#define FSL_SAI_RCR4 0x90 /* SAI Receive Configuration 4 */
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#define FSL_SAI_RCR5 0x94 /* SAI Receive Configuration 5 */
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#define FSL_SAI_RDR 0xa0 /* SAI Receive Data */
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#define FSL_SAI_RFR 0xc0 /* SAI Receive FIFO */
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#define FSL_SAI_RMR 0xe0 /* SAI Receive Mask */
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#define FSL_SAI_xCSR(tx) (tx ? FSL_SAI_TCSR : FSL_SAI_RCSR)
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#define FSL_SAI_xCR1(tx) (tx ? FSL_SAI_TCR1 : FSL_SAI_RCR1)
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#define FSL_SAI_xCR2(tx) (tx ? FSL_SAI_TCR2 : FSL_SAI_RCR2)
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#define FSL_SAI_xCR3(tx) (tx ? FSL_SAI_TCR3 : FSL_SAI_RCR3)
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#define FSL_SAI_xCR4(tx) (tx ? FSL_SAI_TCR4 : FSL_SAI_RCR4)
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#define FSL_SAI_xCR5(tx) (tx ? FSL_SAI_TCR5 : FSL_SAI_RCR5)
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#define FSL_SAI_xDR(tx) (tx ? FSL_SAI_TDR : FSL_SAI_RDR)
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#define FSL_SAI_xFR(tx) (tx ? FSL_SAI_TFR : FSL_SAI_RFR)
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#define FSL_SAI_xMR(tx) (tx ? FSL_SAI_TMR : FSL_SAI_RMR)
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/* SAI Transmit/Receive Control Register */
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#define FSL_SAI_CSR_TERE BIT(31)
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#define FSL_SAI_CSR_FR BIT(25)
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#define FSL_SAI_CSR_SR BIT(24)
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#define FSL_SAI_CSR_xF_SHIFT 16
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#define FSL_SAI_CSR_xF_W_SHIFT 18
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#define FSL_SAI_CSR_xF_MASK (0x1f << FSL_SAI_CSR_xF_SHIFT)
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#define FSL_SAI_CSR_xF_W_MASK (0x7 << FSL_SAI_CSR_xF_W_SHIFT)
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#define FSL_SAI_CSR_WSF BIT(20)
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#define FSL_SAI_CSR_SEF BIT(19)
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#define FSL_SAI_CSR_FEF BIT(18)
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#define FSL_SAI_CSR_FWF BIT(17)
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#define FSL_SAI_CSR_FRF BIT(16)
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#define FSL_SAI_CSR_xIE_SHIFT 8
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#define FSL_SAI_CSR_xIE_MASK (0x1f << FSL_SAI_CSR_xIE_SHIFT)
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#define FSL_SAI_CSR_WSIE BIT(12)
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#define FSL_SAI_CSR_SEIE BIT(11)
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#define FSL_SAI_CSR_FEIE BIT(10)
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#define FSL_SAI_CSR_FWIE BIT(9)
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#define FSL_SAI_CSR_FRIE BIT(8)
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#define FSL_SAI_CSR_FRDE BIT(0)
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/* SAI Transmit and Receive Configuration 1 Register */
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#define FSL_SAI_CR1_RFW_MASK 0x1f
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/* SAI Transmit and Receive Configuration 2 Register */
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#define FSL_SAI_CR2_SYNC BIT(30)
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#define FSL_SAI_CR2_MSEL_MASK (0x3 << 26)
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#define FSL_SAI_CR2_MSEL_BUS 0
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#define FSL_SAI_CR2_MSEL_MCLK1 BIT(26)
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#define FSL_SAI_CR2_MSEL_MCLK2 BIT(27)
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#define FSL_SAI_CR2_MSEL_MCLK3 (BIT(26) | BIT(27))
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#define FSL_SAI_CR2_MSEL(ID) ((ID) << 26)
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#define FSL_SAI_CR2_BCP BIT(25)
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#define FSL_SAI_CR2_BCD_MSTR BIT(24)
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#define FSL_SAI_CR2_DIV_MASK 0xff
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/* SAI Transmit and Receive Configuration 3 Register */
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#define FSL_SAI_CR3_TRCE BIT(16)
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#define FSL_SAI_CR3_WDFL(x) (x)
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#define FSL_SAI_CR3_WDFL_MASK 0x1f
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/* SAI Transmit and Receive Configuration 4 Register */
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#define FSL_SAI_CR4_FRSZ(x) (((x) - 1) << 16)
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#define FSL_SAI_CR4_FRSZ_MASK (0x1f << 16)
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#define FSL_SAI_CR4_SYWD(x) (((x) - 1) << 8)
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#define FSL_SAI_CR4_SYWD_MASK (0x1f << 8)
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#define FSL_SAI_CR4_MF BIT(4)
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#define FSL_SAI_CR4_FSE BIT(3)
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#define FSL_SAI_CR4_FSP BIT(1)
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#define FSL_SAI_CR4_FSD_MSTR BIT(0)
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/* SAI Transmit and Receive Configuration 5 Register */
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#define FSL_SAI_CR5_WNW(x) (((x) - 1) << 24)
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#define FSL_SAI_CR5_WNW_MASK (0x1f << 24)
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#define FSL_SAI_CR5_W0W(x) (((x) - 1) << 16)
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#define FSL_SAI_CR5_W0W_MASK (0x1f << 16)
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#define FSL_SAI_CR5_FBT(x) ((x) << 8)
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#define FSL_SAI_CR5_FBT_MASK (0x1f << 8)
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/* SAI type */
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#define FSL_SAI_DMA BIT(0)
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#define FSL_SAI_USE_AC97 BIT(1)
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#define FSL_SAI_NET BIT(2)
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#define FSL_SAI_TRA_SYN BIT(3)
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#define FSL_SAI_REC_SYN BIT(4)
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#define FSL_SAI_USE_I2S_SLAVE BIT(5)
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#define FSL_FMT_TRANSMITTER 0
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#define FSL_FMT_RECEIVER 1
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/* SAI clock sources */
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#define FSL_SAI_CLK_BUS 0
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#define FSL_SAI_CLK_MAST1 1
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#define FSL_SAI_CLK_MAST2 2
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#define FSL_SAI_CLK_MAST3 3
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#define FSL_SAI_MCLK_MAX 4
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/* SAI data transfer numbers per DMA request */
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#define FSL_SAI_MAXBURST_TX 6
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#define FSL_SAI_MAXBURST_RX 6
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struct fsl_sai {
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struct platform_device *pdev;
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struct regmap *regmap;
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struct clk *bus_clk;
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struct clk *mclk_clk[FSL_SAI_MCLK_MAX];
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bool is_slave_mode;
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bool is_lsb_first;
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bool is_dsp_mode;
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bool sai_on_imx;
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bool synchronous[2];
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unsigned int mclk_id[2];
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unsigned int mclk_streams;
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unsigned int slots;
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unsigned int slot_width;
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struct snd_dmaengine_dai_dma_data dma_params_rx;
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struct snd_dmaengine_dai_dma_data dma_params_tx;
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};
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#define TX 1
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#define RX 0
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#endif /* __FSL_SAI_H */
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