/*
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* linux/arch/unicore32/mm/cache-ucv2.S
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Copyright (C) 2001-2010 GUAN Xue-tao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This is the "shell" of the UniCore-v2 processor support.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/page.h>
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#include "proc-macros.S"
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/*
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* __cpuc_flush_icache_all()
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* __cpuc_flush_kern_all()
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* __cpuc_flush_user_all()
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*
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* Flush the entire cache.
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*/
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ENTRY(__cpuc_flush_icache_all)
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/*FALLTHROUGH*/
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ENTRY(__cpuc_flush_kern_all)
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/*FALLTHROUGH*/
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ENTRY(__cpuc_flush_user_all)
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mov r0, #0
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movc p0.c5, r0, #14 @ Dcache flush all
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nop8
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mov r0, #0
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movc p0.c5, r0, #20 @ Icache invalidate all
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nop8
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mov pc, lr
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/*
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* __cpuc_flush_user_range(start, end, flags)
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*
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* Flush a range of TLB entries in the specified address space.
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*
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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* - flags - vm_area_struct flags describing address space
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*/
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ENTRY(__cpuc_flush_user_range)
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cxor.a r2, #0
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beq __cpuc_dma_flush_range
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#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE
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andn r0, r0, #CACHE_LINESIZE - 1 @ Safety check
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sub r1, r1, r0
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csub.a r1, #MAX_AREA_SIZE
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bsg 2f
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andn r1, r1, #CACHE_LINESIZE - 1
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add r1, r1, #CACHE_LINESIZE
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101: dcacheline_flush r0, r11, r12
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add r0, r0, #CACHE_LINESIZE
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sub.a r1, r1, #CACHE_LINESIZE
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bns 101b
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b 3f
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#endif
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2: mov ip, #0
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movc p0.c5, ip, #14 @ Dcache flush all
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nop8
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3: mov ip, #0
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movc p0.c5, ip, #20 @ Icache invalidate all
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nop8
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mov pc, lr
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/*
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* __cpuc_coherent_kern_range(start,end)
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* __cpuc_coherent_user_range(start,end)
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*
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* Ensure that the I and D caches are coherent within specified
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* region. This is typically used when code has been written to
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* a memory region, and will be executed.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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ENTRY(__cpuc_coherent_kern_range)
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/* FALLTHROUGH */
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ENTRY(__cpuc_coherent_user_range)
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#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE
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andn r0, r0, #CACHE_LINESIZE - 1 @ Safety check
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sub r1, r1, r0
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csub.a r1, #MAX_AREA_SIZE
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bsg 2f
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andn r1, r1, #CACHE_LINESIZE - 1
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add r1, r1, #CACHE_LINESIZE
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@ r0 va2pa r10
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mov r9, #PAGE_SZ
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sub r9, r9, #1 @ PAGE_MASK
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101: va2pa r0, r10, r11, r12, r13, 2f @ r10 is PA
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b 103f
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102: cand.a r0, r9
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beq 101b
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103: movc p0.c5, r10, #11 @ Dcache clean line of R10
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nop8
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add r0, r0, #CACHE_LINESIZE
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add r10, r10, #CACHE_LINESIZE
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sub.a r1, r1, #CACHE_LINESIZE
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bns 102b
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b 3f
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#endif
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2: mov ip, #0
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movc p0.c5, ip, #10 @ Dcache clean all
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nop8
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3: mov ip, #0
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movc p0.c5, ip, #20 @ Icache invalidate all
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nop8
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mov pc, lr
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/*
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* __cpuc_flush_kern_dcache_area(void *addr, size_t size)
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*
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* - addr - kernel address
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* - size - region size
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*/
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ENTRY(__cpuc_flush_kern_dcache_area)
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mov ip, #0
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movc p0.c5, ip, #14 @ Dcache flush all
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nop8
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mov pc, lr
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/*
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* __cpuc_dma_clean_range(start,end)
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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ENTRY(__cpuc_dma_clean_range)
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#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE
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andn r0, r0, #CACHE_LINESIZE - 1
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sub r1, r1, r0
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andn r1, r1, #CACHE_LINESIZE - 1
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add r1, r1, #CACHE_LINESIZE
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csub.a r1, #MAX_AREA_SIZE
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bsg 2f
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@ r0 va2pa r10
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mov r9, #PAGE_SZ
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sub r9, r9, #1 @ PAGE_MASK
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101: va2pa r0, r10, r11, r12, r13, 2f @ r10 is PA
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b 1f
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102: cand.a r0, r9
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beq 101b
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1: movc p0.c5, r10, #11 @ Dcache clean line of R10
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nop8
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add r0, r0, #CACHE_LINESIZE
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add r10, r10, #CACHE_LINESIZE
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sub.a r1, r1, #CACHE_LINESIZE
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bns 102b
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mov pc, lr
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#endif
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2: mov ip, #0
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movc p0.c5, ip, #10 @ Dcache clean all
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nop8
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mov pc, lr
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/*
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* __cpuc_dma_inv_range(start,end)
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* __cpuc_dma_flush_range(start,end)
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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__cpuc_dma_inv_range:
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/* FALLTHROUGH */
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ENTRY(__cpuc_dma_flush_range)
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#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE
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andn r0, r0, #CACHE_LINESIZE - 1
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sub r1, r1, r0
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andn r1, r1, #CACHE_LINESIZE - 1
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add r1, r1, #CACHE_LINESIZE
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csub.a r1, #MAX_AREA_SIZE
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bsg 2f
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@ r0 va2pa r10
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101: dcacheline_flush r0, r11, r12
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add r0, r0, #CACHE_LINESIZE
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sub.a r1, r1, #CACHE_LINESIZE
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bns 101b
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mov pc, lr
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#endif
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2: mov ip, #0
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movc p0.c5, ip, #14 @ Dcache flush all
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nop8
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mov pc, lr
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