/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* arch/s390/kernel/base.S
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*
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* Copyright IBM Corp. 2006, 2007
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* Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
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* Michael Holzheu <holzheu@de.ibm.com>
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*/
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#include <linux/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/nospec-insn.h>
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#include <asm/ptrace.h>
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#include <asm/sigp.h>
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GEN_BR_THUNK %r9
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GEN_BR_THUNK %r14
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ENTRY(s390_base_mcck_handler)
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basr %r13,0
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0: lg %r15,__LC_PANIC_STACK # load panic stack
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aghi %r15,-STACK_FRAME_OVERHEAD
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larl %r1,s390_base_mcck_handler_fn
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lg %r9,0(%r1)
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ltgr %r9,%r9
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jz 1f
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BASR_EX %r14,%r9
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1: la %r1,4095
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lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)
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lpswe __LC_MCK_OLD_PSW
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.section .bss
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.align 8
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.globl s390_base_mcck_handler_fn
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s390_base_mcck_handler_fn:
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.quad 0
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.previous
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ENTRY(s390_base_ext_handler)
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stmg %r0,%r15,__LC_SAVE_AREA_ASYNC
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basr %r13,0
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0: aghi %r15,-STACK_FRAME_OVERHEAD
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larl %r1,s390_base_ext_handler_fn
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lg %r9,0(%r1)
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ltgr %r9,%r9
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jz 1f
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BASR_EX %r14,%r9
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1: lmg %r0,%r15,__LC_SAVE_AREA_ASYNC
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ni __LC_EXT_OLD_PSW+1,0xfd # clear wait state bit
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lpswe __LC_EXT_OLD_PSW
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.section .bss
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.align 8
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.globl s390_base_ext_handler_fn
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s390_base_ext_handler_fn:
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.quad 0
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.previous
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ENTRY(s390_base_pgm_handler)
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stmg %r0,%r15,__LC_SAVE_AREA_SYNC
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basr %r13,0
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0: aghi %r15,-STACK_FRAME_OVERHEAD
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larl %r1,s390_base_pgm_handler_fn
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lg %r9,0(%r1)
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ltgr %r9,%r9
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jz 1f
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BASR_EX %r14,%r9
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lmg %r0,%r15,__LC_SAVE_AREA_SYNC
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lpswe __LC_PGM_OLD_PSW
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1: lpswe disabled_wait_psw-0b(%r13)
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.align 8
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disabled_wait_psw:
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.quad 0x0002000180000000,0x0000000000000000 + s390_base_pgm_handler
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.section .bss
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.align 8
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.globl s390_base_pgm_handler_fn
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s390_base_pgm_handler_fn:
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.quad 0
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.previous
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#
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# Calls diag 308 subcode 1 and continues execution
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#
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ENTRY(diag308_reset)
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larl %r4,.Lctlregs # Save control registers
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stctg %c0,%c15,0(%r4)
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lg %r2,0(%r4) # Disable lowcore protection
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nilh %r2,0xefff
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larl %r4,.Lctlreg0
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stg %r2,0(%r4)
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lctlg %c0,%c0,0(%r4)
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larl %r4,.Lfpctl # Floating point control register
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stfpc 0(%r4)
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larl %r4,.Lprefix # Save prefix register
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stpx 0(%r4)
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larl %r4,.Lprefix_zero # Set prefix register to 0
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spx 0(%r4)
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larl %r4,.Lcontinue_psw # Save PSW flags
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epsw %r2,%r3
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stm %r2,%r3,0(%r4)
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larl %r4,.Lrestart_psw # Setup restart PSW at absolute 0
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lghi %r3,0
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lg %r4,0(%r4) # Save PSW
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sturg %r4,%r3 # Use sturg, because of large pages
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lghi %r1,1
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lghi %r0,0
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diag %r0,%r1,0x308
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.Lrestart_part2:
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lhi %r0,0 # Load r0 with zero
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lhi %r1,2 # Use mode 2 = ESAME (dump)
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sigp %r1,%r0,SIGP_SET_ARCHITECTURE # Switch to ESAME mode
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sam64 # Switch to 64 bit addressing mode
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larl %r4,.Lctlregs # Restore control registers
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lctlg %c0,%c15,0(%r4)
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larl %r4,.Lfpctl # Restore floating point ctl register
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lfpc 0(%r4)
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larl %r4,.Lprefix # Restore prefix register
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spx 0(%r4)
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larl %r4,.Lcontinue_psw # Restore PSW flags
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lpswe 0(%r4)
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.Lcontinue:
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BR_EX %r14
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.align 16
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.Lrestart_psw:
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.long 0x00080000,0x80000000 + .Lrestart_part2
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.section .data..nosave,"aw",@progbits
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.align 8
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.Lcontinue_psw:
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.quad 0,.Lcontinue
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.previous
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.section .bss
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.align 8
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.Lctlreg0:
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.quad 0
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.Lctlregs:
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.rept 16
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.quad 0
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.endr
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.Lfpctl:
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.long 0
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.Lprefix:
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.long 0
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.Lprefix_zero:
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.long 0
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.previous
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