/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_NOHASH_64_PGTABLE_4K_H
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#define _ASM_POWERPC_NOHASH_64_PGTABLE_4K_H
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#include <asm-generic/5level-fixup.h>
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/*
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* Entries per page directory level. The PTE level must use a 64b record
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* for each page table entry. The PMD and PGD level use a 32b record for
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* each entry by assuming that each entry is page aligned.
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*/
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#define PTE_INDEX_SIZE 9
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#define PMD_INDEX_SIZE 7
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#define PUD_INDEX_SIZE 9
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#define PGD_INDEX_SIZE 9
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#ifndef __ASSEMBLY__
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#define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE)
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#define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
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#define PUD_TABLE_SIZE (sizeof(pud_t) << PUD_INDEX_SIZE)
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#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
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#endif /* __ASSEMBLY__ */
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#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
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#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
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#define PTRS_PER_PUD (1 << PUD_INDEX_SIZE)
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#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
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/* PMD_SHIFT determines what a second-level page table entry can map */
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#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
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#define PMD_SIZE (1UL << PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE-1))
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/* PUD_SHIFT determines what a third-level page table entry can map */
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#define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
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#define PUD_SIZE (1UL << PUD_SHIFT)
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#define PUD_MASK (~(PUD_SIZE-1))
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/* PGDIR_SHIFT determines what a fourth-level page table entry can map */
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#define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE)
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/* Bits to mask out from a PMD to get to the PTE page */
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#define PMD_MASKED_BITS 0
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/* Bits to mask out from a PUD to get to the PMD page */
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#define PUD_MASKED_BITS 0
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/* Bits to mask out from a PGD to get to the PUD page */
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#define PGD_MASKED_BITS 0
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/*
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* 4-level page tables related bits
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*/
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#define pgd_none(pgd) (!pgd_val(pgd))
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#define pgd_bad(pgd) (pgd_val(pgd) == 0)
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#define pgd_present(pgd) (pgd_val(pgd) != 0)
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#define pgd_page_vaddr(pgd) (pgd_val(pgd) & ~PGD_MASKED_BITS)
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#ifndef __ASSEMBLY__
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static inline void pgd_clear(pgd_t *pgdp)
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{
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*pgdp = __pgd(0);
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}
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static inline pte_t pgd_pte(pgd_t pgd)
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{
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return __pte(pgd_val(pgd));
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}
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static inline pgd_t pte_pgd(pte_t pte)
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{
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return __pgd(pte_val(pte));
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}
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extern struct page *pgd_page(pgd_t pgd);
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#endif /* !__ASSEMBLY__ */
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#define pud_offset(pgdp, addr) \
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(((pud_t *) pgd_page_vaddr(*(pgdp))) + \
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(((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)))
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#define pud_ERROR(e) \
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pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
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/*
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* On all 4K setups, remap_4k_pfn() equates to remap_pfn_range() */
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#define remap_4k_pfn(vma, addr, pfn, prot) \
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remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))
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#endif /* _ _ASM_POWERPC_NOHASH_64_PGTABLE_4K_H */
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