/*
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* T2080PCIe-RDB Board Device Tree Source
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*
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* Copyright 2014 - 2015 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/include/ "t208xsi-pre.dtsi"
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/include/ "t208xrdb.dtsi"
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/ {
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model = "fsl,T2080RDB";
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compatible = "fsl,T2080RDB";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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rio: rapidio@ffe0c0000 {
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reg = <0xf 0xfe0c0000 0 0x11000>;
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port1 {
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ranges = <0 0 0xc 0x20000000 0 0x10000000>;
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};
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port2 {
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ranges = <0 0 0xc 0x30000000 0 0x10000000>;
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};
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};
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};
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&soc {
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fman@400000 {
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ethernet@e0000 {
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phy-handle = <&xg_aq1202_phy3>;
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phy-connection-type = "xgmii";
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};
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ethernet@e2000 {
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phy-handle = <&xg_aq1202_phy4>;
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phy-connection-type = "xgmii";
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};
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ethernet@e4000 {
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phy-handle = <&rgmii_phy1>;
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phy-connection-type = "rgmii";
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};
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ethernet@e6000 {
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phy-handle = <&rgmii_phy2>;
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phy-connection-type = "rgmii";
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};
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ethernet@f0000 {
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phy-handle = <&xg_cs4315_phy1>;
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phy-connection-type = "xgmii";
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};
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ethernet@f2000 {
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phy-handle = <&xg_cs4315_phy2>;
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phy-connection-type = "xgmii";
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};
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mdio@fc000 {
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rgmii_phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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rgmii_phy2: ethernet-phy@2 {
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reg = <0x2>;
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};
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};
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mdio@fd000 {
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xg_cs4315_phy1: ethernet-phy@c {
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compatible = "ethernet-phy-id13e5.1002";
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reg = <0xc>;
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};
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xg_cs4315_phy2: ethernet-phy@d {
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compatible = "ethernet-phy-id13e5.1002";
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reg = <0xd>;
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};
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xg_aq1202_phy3: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x0>;
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};
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xg_aq1202_phy4: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x1>;
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};
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};
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};
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};
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/include/ "t2080si-post.dtsi"
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