// SPDX-License-Identifier: GPL-2.0
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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reg = <0>;
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model = "ti,c64x+";
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};
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cpu@1 {
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device_type = "cpu";
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reg = <1>;
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model = "ti,c64x+";
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};
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cpu@2 {
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device_type = "cpu";
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reg = <2>;
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model = "ti,c64x+";
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};
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};
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soc {
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compatible = "simple-bus";
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model = "tms320c6474";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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core_pic: interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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compatible = "ti,c64x+core-pic";
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};
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megamod_pic: interrupt-controller@1800000 {
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compatible = "ti,c64x+megamod-pic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x1800000 0x1000>;
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interrupt-parent = <&core_pic>;
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};
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cache-controller@1840000 {
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compatible = "ti,c64x+cache";
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reg = <0x01840000 0x8400>;
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};
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timer3: timer@2940000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x04 >;
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reg = <0x2940000 0x40>;
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};
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timer4: timer@2950000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x02 >;
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reg = <0x2950000 0x40>;
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};
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timer5: timer@2960000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x01 >;
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reg = <0x2960000 0x40>;
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};
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device-state-controller@2880800 {
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compatible = "ti,c64x+dscr";
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reg = <0x02880800 0x400>;
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ti,dscr-devstat = <0x004>;
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ti,dscr-silicon-rev = <0x014 28 0xf>;
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ti,dscr-mac-fuse-regs = <0x34 3 4 5 6
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0x38 0 0 1 2>;
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};
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clock-controller@29a0000 {
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compatible = "ti,c6474-pll", "ti,c64x+pll";
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reg = <0x029a0000 0x200>;
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ti,c64x+pll-bypass-delay = <120>;
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ti,c64x+pll-reset-delay = <30000>;
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ti,c64x+pll-lock-delay = <60000>;
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};
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};
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};
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