// SPDX-License-Identifier: GPL-2.0
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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model = "ti,c64x+";
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reg = <0>;
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};
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};
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soc {
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compatible = "simple-bus";
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model = "tms320c6455";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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core_pic: interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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compatible = "ti,c64x+core-pic";
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};
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/*
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* Megamodule interrupt controller
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*/
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megamod_pic: interrupt-controller@1800000 {
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compatible = "ti,c64x+megamod-pic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x1800000 0x1000>;
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interrupt-parent = <&core_pic>;
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};
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cache-controller@1840000 {
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compatible = "ti,c64x+cache";
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reg = <0x01840000 0x8400>;
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};
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emifa@70000000 {
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compatible = "ti,c64x+emifa", "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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reg = <0x70000000 0x100>;
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ranges = <0x2 0x0 0xa0000000 0x00000008
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0x3 0x0 0xb0000000 0x00400000
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0x4 0x0 0xc0000000 0x10000000
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0x5 0x0 0xD0000000 0x10000000>;
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ti,dscr-dev-enable = <13>;
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ti,emifa-burst-priority = <255>;
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ti,emifa-ce-config = <0x00240120
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0x00240120
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0x00240122
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0x00240122>;
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};
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timer1: timer@2980000 {
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compatible = "ti,c64x+timer64";
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reg = <0x2980000 0x40>;
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ti,dscr-dev-enable = <4>;
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};
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clock-controller@029a0000 {
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compatible = "ti,c6455-pll", "ti,c64x+pll";
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reg = <0x029a0000 0x200>;
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ti,c64x+pll-bypass-delay = <1440>;
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ti,c64x+pll-reset-delay = <15360>;
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ti,c64x+pll-lock-delay = <24000>;
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};
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device-state-config-regs@2a80000 {
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compatible = "ti,c64x+dscr";
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reg = <0x02a80000 0x41000>;
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ti,dscr-devstat = <0>;
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ti,dscr-silicon-rev = <8 28 0xf>;
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ti,dscr-rmii-resets = <0 0x40020 0x00040000>;
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ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>;
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ti,dscr-devstate-ctl-regs =
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<0 12 0x40008 1 0 0 2
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12 1 0x40008 3 0 30 2
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13 2 0x4002c 1 0xffffffff 0 1>;
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ti,dscr-devstate-stat-regs =
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<0 10 0x40014 1 0 0 3
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10 2 0x40018 1 0 0 3>;
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};
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};
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};
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