// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
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#include "rk3399.dtsi"
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/ {
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compatible = "rockchip,rk3399pro";
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xin32k: xin32k {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "xin32k";
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#clock-cells = <0>;
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};
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};
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&dfi {
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status = "okay";
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};
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&dmc {
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status = "okay";
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center-supply = <&vdd_log>;
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upthreshold = <40>;
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downdifferential = <20>;
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system-status-freq = <
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/*system status freq(KHz)*/
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SYS_STATUS_NORMAL 800000
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SYS_STATUS_REBOOT 528000
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SYS_STATUS_SUSPEND 200000
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SYS_STATUS_VIDEO_1080P 200000
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SYS_STATUS_VIDEO_4K 600000
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SYS_STATUS_VIDEO_4K_10B 800000
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SYS_STATUS_PERFORMANCE 800000
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SYS_STATUS_BOOST 400000
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SYS_STATUS_DUALVIEW 600000
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SYS_STATUS_ISP 600000
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>;
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vop-pn-msch-readlatency = <
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/* plane_number readlatency */
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0 0
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4 0x20
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>;
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vop-bw-dmc-freq = <
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/* min_bw(MB/s) max_bw(MB/s) freq(KHz) */
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0 762 200000
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763 1893 400000
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1894 3012 528000
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3013 99999 800000
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>;
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auto-min-freq = <200000>;
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};
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&emmc_phy {
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status = "okay";
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};
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&pcie_phy {
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status = "okay";
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};
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&pcie0 {
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ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
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num-lanes = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_clkreqn_cpm>;
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status = "okay";
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};
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&sdhci {
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bus-width = <8>;
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mmc-hs400-1_8v;
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supports-emmc;
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non-removable;
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keep-power-in-suspend;
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mmc-hs400-enhanced-strobe;
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status = "okay";
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};
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&sdio0 {
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clock-frequency = <150000000>;
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clock-freq-min-max = <200000 150000000>;
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supports-sdio;
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bus-width = <4>;
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disable-wp;
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cap-sd-highspeed;
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cap-sdio-irq;
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keep-power-in-suspend;
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mmc-pwrseq = <&sdio_pwrseq>;
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non-removable;
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num-slots = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
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sd-uhs-sdr104;
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status = "okay";
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};
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&sdmmc {
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clock-frequency = <150000000>;
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clock-freq-min-max = <400000 150000000>;
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supports-sd;
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bus-width = <4>;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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disable-wp;
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num-slots = <1>;
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vqmmc-supply = <&vccio_sd>;
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
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status = "okay";
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};
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