/*
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* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/ {
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chosen: chosen {
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bootargs = "earlycon=uart8250,mmio32,0xff690000 firmware_class.path=/system/vendor/firmware";
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};
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fiq_debugger: fiq-debugger {
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compatible = "rockchip,fiq-debugger";
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rockchip,serial-id = <2>;
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rockchip,wake-irq = <0>;
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rockchip,irq-mode-enable = <0>; /* If enable uart uses irq instead of fiq */
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rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_xfer>;
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interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; /* signal irq */
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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drm_logo: drm-logo@00000000 {
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compatible = "rockchip,drm-logo";
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reg = <0x0 0x0 0x0 0x0>;
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};
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ramoops: ramoops@110000 {
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compatible = "ramoops";
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reg = <0x0 0x110000 0x0 0xf0000>;
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record-size = <0x20000>;
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console-size = <0x80000>;
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ftrace-size = <0x00000>;
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pmsg-size = <0x50000>;
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};
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/* global autoconfigured region for contiguous allocations */
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x2000000>;
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linux,cma-default;
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};
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};
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ion {
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compatible = "rockchip,ion";
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#address-cells = <1>;
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#size-cells = <0>;
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cma-heap {
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reg = <0x00000000 0x2800000>;
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};
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system-heap {
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};
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};
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firmware {
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firmware_android: android {};
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};
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rga@ff920000 {
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compatible = "rockchip,rga2";
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dev_mode = <1>;
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reg = <0x0 0xff920000 0x0 0x1000>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
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clock-names = "aclk_rga", "hclk_rga", "clk_rga";
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status = "okay";
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};
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};
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&cluster1_opp {
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rockchip,avs = <1>;
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};
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&display_subsystem {
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status = "okay";
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logo-memory-region = <&drm_logo>;
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route {
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route_dsi: route-dsi {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vop_out_dsi>;
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};
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route_edp: route-edp {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vop_out_edp>;
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};
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route_hdmi: route-hdmi {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vop_out_hdmi>;
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};
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route_lvds: route-lvds {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vop_out_lvds>;
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};
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route_rgb: route-rgb {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vop_out_rgb>;
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};
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};
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};
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&dsi {
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panel@0 {
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reg = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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panel_in_dsi: endpoint {
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remote-endpoint = <&dsi_out_panel>;
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};
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};
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};
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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dsi_out_panel: endpoint {
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remote-endpoint = <&panel_in_dsi>;
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};
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};
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};
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};
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&hevc {
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status = "okay";
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};
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&hevc_mmu {
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status = "okay";
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};
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&iep {
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status = "okay";
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};
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&iep_mmu {
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status = "okay";
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};
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&mailbox {
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status = "okay";
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};
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&mailbox_scpi {
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status = "okay";
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};
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&mpp_srv {
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status = "okay";
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};
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&vdpu {
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status = "okay";
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};
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&vepu {
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status = "okay";
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};
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&vpu_mmu {
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status = "okay";
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};
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&vop {
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support-multi-area;
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status = "okay";
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};
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&vop_mmu {
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status = "okay";
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};
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&isp {
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status = "okay";
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};
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&isp_mmu {
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status = "okay";
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};
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&cif {
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status = "okay";
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};
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&rng {
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status = "okay";
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};
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&vip_mmu {
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status = "okay";
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};
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&video_phy {
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status = "okay";
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};
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&usb_otg {
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status = "okay";
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};
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&pinctrl {
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isp {
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cif_clkout: cif-clkout {
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rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;//cif_clkout
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};
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isp_dvp_d2d9: isp-dvp-d2d9 {
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rockchip,pins =
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<1 RK_PA0 1 &pcfg_pull_none>,//cif_data2
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<1 RK_PA1 1 &pcfg_pull_none>,//cif_data3
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<1 RK_PA2 1 &pcfg_pull_none>,//cif_data4
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<1 RK_PA3 1 &pcfg_pull_none>,//cif_data5
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<1 RK_PA4 1 &pcfg_pull_none>,//cif_data6
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<1 RK_PA5 1 &pcfg_pull_none>,//cif_data7
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<1 RK_PA6 1 &pcfg_pull_none>,//cif_data8
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<1 RK_PA7 1 &pcfg_pull_none>,//cif_data9
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<1 RK_PB0 1 &pcfg_pull_none>,//cif_sync
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<1 RK_PB1 1 &pcfg_pull_none>,//cif_href
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<1 RK_PB2 1 &pcfg_pull_none>,//cif_clkin
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<1 RK_PB3 1 &pcfg_pull_none>;//cif_clkout
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};
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isp_dvp_d0d1: isp-dvp-d0d1 {
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rockchip,pins =
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<1 RK_PB4 1 &pcfg_pull_none>,//cif_data0
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<1 RK_PB5 1 &pcfg_pull_none>;//cif_data1
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};
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isp_dvp_d10d11:isp_d10d11 {
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rockchip,pins =
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<1 RK_PB6 1 &pcfg_pull_none>,//cif_data10
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<1 RK_PB7 1 &pcfg_pull_none>;//cif_data11
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};
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isp_dvp_d0d7: isp-dvp-d0d7 {
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rockchip,pins =
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<1 RK_PB4 1 &pcfg_pull_none>,//cif_data0
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<1 RK_PB5 1 &pcfg_pull_none>,//cif_data1
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<1 RK_PA0 1 &pcfg_pull_none>,//cif_data2
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<1 RK_PA1 1 &pcfg_pull_none>,//cif_data3
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<1 RK_PA2 1 &pcfg_pull_none>,//cif_data4
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<1 RK_PA3 1 &pcfg_pull_none>,//cif_data5
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<1 RK_PA4 1 &pcfg_pull_none>,//cif_data6
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<1 RK_PA5 1 &pcfg_pull_none>;//cif_data7
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};
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isp_dvp_d4d11: isp-dvp-d4d11 {
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rockchip,pins =
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<1 RK_PA2 1 &pcfg_pull_none>,//cif_data4
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<1 RK_PA3 1 &pcfg_pull_none>,//cif_data5
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<1 RK_PA4 1 &pcfg_pull_none>,//cif_data6
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<1 RK_PA5 1 &pcfg_pull_none>,//cif_data7
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<1 RK_PA6 1 &pcfg_pull_none>,//cif_data8
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<1 RK_PA7 1 &pcfg_pull_none>,//cif_data9
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<1 RK_PB6 1 &pcfg_pull_none>,//cif_data10
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<1 RK_PC1 1 &pcfg_pull_none>;//cif_data11
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};
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isp_shutter: isp-shutter {
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rockchip,pins =
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<3 RK_PC3 2 &pcfg_pull_none>, //SHUTTEREN
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<3 RK_PC6 2 &pcfg_pull_none>;//SHUTTERTRIG
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};
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isp_flash_trigger: isp-flash-trigger {
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rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
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};
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isp_prelight: isp-prelight {
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rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
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};
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isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
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rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
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};
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};
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};
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