/*
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* Copyright(c) 2015 EZchip Technologies.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in
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* the file called "COPYING".
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <asm/mach_desc.h>
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#include <plat/mtm.h>
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static void __init eznps_configure_msu(void)
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{
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int cpu;
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struct nps_host_reg_msu_en_cfg msu_en_cfg = {.value = 0};
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msu_en_cfg.msu_en = 1;
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msu_en_cfg.ipi_en = 1;
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msu_en_cfg.gim_0_en = 1;
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msu_en_cfg.gim_1_en = 1;
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/* enable IPI and GIM messages on all clusters */
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for (cpu = 0 ; cpu < eznps_max_cpus; cpu += eznps_cpus_per_cluster)
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iowrite32be(msu_en_cfg.value,
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nps_host_reg(cpu, NPS_MSU_BLKID, NPS_MSU_EN_CFG));
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}
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static void __init eznps_configure_gim(void)
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{
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u32 reg_value;
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u32 gim_int_lines;
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struct nps_host_reg_gim_p_int_dst gim_p_int_dst = {.value = 0};
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gim_int_lines = NPS_GIM_UART_LINE;
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gim_int_lines |= NPS_GIM_DBG_LAN_EAST_TX_DONE_LINE;
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gim_int_lines |= NPS_GIM_DBG_LAN_EAST_RX_RDY_LINE;
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gim_int_lines |= NPS_GIM_DBG_LAN_WEST_TX_DONE_LINE;
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gim_int_lines |= NPS_GIM_DBG_LAN_WEST_RX_RDY_LINE;
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/*
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* IRQ polarity
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* low or high level
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* negative or positive edge
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*/
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reg_value = ioread32be(REG_GIM_P_INT_POL_0);
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reg_value &= ~gim_int_lines;
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iowrite32be(reg_value, REG_GIM_P_INT_POL_0);
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/* IRQ type level or edge */
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reg_value = ioread32be(REG_GIM_P_INT_SENS_0);
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reg_value |= NPS_GIM_DBG_LAN_EAST_TX_DONE_LINE;
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reg_value |= NPS_GIM_DBG_LAN_WEST_TX_DONE_LINE;
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iowrite32be(reg_value, REG_GIM_P_INT_SENS_0);
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/*
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* GIM interrupt select type for
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* dbg_lan TX and RX interrupts
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* should be type 1
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* type 0 = IRQ line 6
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* type 1 = IRQ line 7
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*/
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gim_p_int_dst.is = 1;
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iowrite32be(gim_p_int_dst.value, REG_GIM_P_INT_DST_10);
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iowrite32be(gim_p_int_dst.value, REG_GIM_P_INT_DST_11);
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iowrite32be(gim_p_int_dst.value, REG_GIM_P_INT_DST_25);
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iowrite32be(gim_p_int_dst.value, REG_GIM_P_INT_DST_26);
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/*
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* CTOP IRQ lines should be defined
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* as blocking in GIM
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*/
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iowrite32be(gim_int_lines, REG_GIM_P_INT_BLK_0);
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/* enable CTOP IRQ lines in GIM */
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iowrite32be(gim_int_lines, REG_GIM_P_INT_EN_0);
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}
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static void __init eznps_early_init(void)
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{
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eznps_configure_msu();
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eznps_configure_gim();
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}
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static const char *eznps_compat[] __initconst = {
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"ezchip,arc-nps",
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NULL,
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};
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MACHINE_START(NPS, "nps")
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.dt_compat = eznps_compat,
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.init_early = eznps_early_init,
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MACHINE_END
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