# SPDX-License-Identifier: GPL-2.0
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#
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# For a description of the syntax of this configuration file,
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# see Documentation/kbuild/kconfig-language.txt.
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#
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menuconfig ARC_PLAT_EZNPS
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bool "\"EZchip\" ARC dev platform"
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depends on ISA_ARCOMPACT
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select CPU_BIG_ENDIAN
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select CLKSRC_NPS if !PHYS_ADDR_T_64BIT
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select EZNPS_GIC
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select EZCHIP_NPS_MANAGEMENT_ENET if ETHERNET
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help
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Support for EZchip development platforms,
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based on ARC700 cores.
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We handle few flavors:
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- Hardware Emulator AKA HE which is FPGA based chassis
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- Simulator based on MetaWare nSIM
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- NPS400 chip based on ASIC
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config EZNPS_MTM_EXT
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bool "ARC-EZchip MTM Extensions"
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select CPUMASK_OFFSTACK
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depends on ARC_PLAT_EZNPS && SMP
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default y
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help
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Here we add new hierarchy for CPUs topology.
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We got:
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Core
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Thread
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At the new thread level each CPU represent one HW thread.
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At highest hierarchy each core contain 16 threads,
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any of them seem like CPU from Linux point of view.
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All threads within same core share the execution unit of the
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core and HW scheduler round robin between them.
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config EZNPS_MEM_ERROR_ALIGN
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bool "ARC-EZchip Memory error as an exception"
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depends on EZNPS_MTM_EXT
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default n
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help
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On the real chip of the NPS, user memory errors are handled
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as a machine check exception, which is fatal, whereas on
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simulator platform for NPS, is handled as a Level 2 interrupt
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(just a stock ARC700) which is recoverable. This option makes
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simulator behave like hardware.
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config EZNPS_SHARED_AUX_REGS
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bool "ARC-EZchip Shared Auxiliary Registers Per Core"
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depends on ARC_PLAT_EZNPS
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default y
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help
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On the real chip of the NPS, auxiliary registers are shared between
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all the cpus of the core, whereas on simulator platform for NPS,
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each cpu has a different set of auxiliary registers. Configuration
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should be unset if auxiliary registers are not shared between the cpus
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of the core, so there will be a need to initialize them per cpu.
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