/*
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* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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/include/ "skeleton_hs_idu.dtsi"
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/ {
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model = "snps,nsim_hs-smp";
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compatible = "snps,nsim_hs";
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interrupt-parent = <&core_intc>;
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chosen {
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bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8 print-fatal-signals=1";
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};
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aliases {
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serial0 = &arcuart0;
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};
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fpga {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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/* child and parent address space 1:1 mapped */
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ranges;
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core_clk: core_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <80000000>;
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};
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core_intc: core-interrupt-controller {
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compatible = "snps,archs-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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idu_intc: idu-interrupt-controller {
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compatible = "snps,archs-idu-intc";
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interrupt-controller;
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interrupt-parent = <&core_intc>;
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#interrupt-cells = <1>;
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};
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arcuart0: serial@c0fc1000 {
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compatible = "snps,arc-uart";
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reg = <0xc0fc1000 0x100>;
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interrupt-parent = <&idu_intc>;
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interrupts = <0>;
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clock-frequency = <80000000>;
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current-speed = <115200>;
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status = "okay";
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};
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arcpct0: pct {
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compatible = "snps,archs-pct";
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#interrupt-cells = <1>;
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interrupts = <20>;
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};
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};
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};
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