Rockchip specific extensions to the Analogix Display Port PHY
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Required properties:
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- compatible : should be one of the following supported values:
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- "rockchip.rk3288-dp-phy"
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- "rockchip.rk3368-dp-phy"
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- clocks: from common clock binding: handle to dp clock.
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of memory mapped region.
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- clock-names: from common clock binding:
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Required elements: "24m"
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- #phy-cells : from the generic PHY bindings, must be 0;
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Optional properties:
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- resets : phandle to the reset of eDP 24m clock domain.
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- reset-names : should be "edp_24m".
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Example:
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grf: syscon@ff770000 {
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compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
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...
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edp_phy: edp-phy {
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compatible = "rockchip,rk3288-dp-phy";
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clocks = <&cru SCLK_EDP_24M>;
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clock-names = "24m";
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#phy-cells = <0>;
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};
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};
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