Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings
|
|
This binding represents the on-chip eFuse OTP controller found on
|
i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX, i.MX6UL and i.MX6SLL SoCs.
|
|
Required properties:
|
- compatible: should be one of
|
"fsl,imx6q-ocotp" (i.MX6Q/D/DL/S),
|
"fsl,imx6sl-ocotp" (i.MX6SL), or
|
"fsl,imx6sx-ocotp" (i.MX6SX),
|
"fsl,imx6ul-ocotp" (i.MX6UL),
|
"fsl,imx7d-ocotp" (i.MX7D/S),
|
"fsl,imx6sll-ocotp" (i.MX6SLL),
|
followed by "syscon".
|
- #address-cells : Should be 1
|
- #size-cells : Should be 1
|
- reg: Should contain the register base and length.
|
- clocks: Should contain a phandle pointing to the gated peripheral clock.
|
|
Optional properties:
|
- read-only: disable write access
|
|
Optional Child nodes:
|
|
- Data cells of ocotp:
|
Detailed bindings are described in bindings/nvmem/nvmem.txt
|
|
Example:
|
ocotp: ocotp@21bc000 {
|
#address-cells = <1>;
|
#size-cells = <1>;
|
compatible = "fsl,imx6sx-ocotp", "syscon";
|
reg = <0x021bc000 0x4000>;
|
clocks = <&clks IMX6SX_CLK_OCOTP>;
|
|
tempmon_calib: calib@38 {
|
reg = <0x38 4>;
|
};
|
|
tempmon_temp_grade: temp-grade@20 {
|
reg = <0x20 4>;
|
};
|
};
|
